IMX28AEC datasheet(6/72 Pages) FREESCALE

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i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 1

Freescale Semiconductor

Table 4 describes the digital and analog modules of the device.

Table 4. i.MX28 Digital and Analog Modules

Block

Mnemonic

Block Name

Subsystem

Brief Description

APBHDMA

AHB to APBH

Bridge with

DMA

System control

The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for

memory-mapped I/O to the APB devices, as well a central DMA facility for

devices on this bus. The bridge provides a peripheral attachment bus running

on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous

to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.)

The DMA controller transfers read and write data to and from each peripheral

on APBH bridge.

APBXDMA

AHB to APBX

Bridge with

DMA

System control

The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for

memory-mapped I/O to the APB devices, as well a central DMA facility for

devices on this bus. The AHB-to-APBX bridge provides a peripheral

attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that

the APBX runs on a crystal-derived clock, as compared to APBH, which is

synchronous to HCLK.) The DMA controller transfers read and write data to

and from each peripheral on APBX bridge.

ARM9 or

ARM926

ARM926EJ-S

CPU

ARM®

The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM

real-time debug modules. It contains the 16-Kbyte L1 instruction cache,

32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.

AUART(5)

Application

UART

interface

Connectivity

peripherals

Each of the UART modules supports the following serial data

transmit/receive protocols and configurations:

• 7- or 8-bit data words, one or two stop bits, programmable parity (even,

odd, or none)

• Programmable baud rates up to 3.25 MHz. This is a higher maximum

baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard

and previous Freescale UART modules. 16-byte FIFO on Tx and 16-byte

FIFO on Rx supporting auto-baud detection

BCH

Bit-correcting

ECC

accelerator

Connectivity

peripherals

The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder

module is capable of correcting from 2 to 20 single bit errors within a block of

data no larger than about 900 bytes (512 bytes is typical) in applications such

as protecting data and resources stored on modern NAND flash devices.

BSI

Boundary

Scan Interface

Connectivity

peripherals

The boundary scan interface is provided to enable board level testing.

There are five pins on the device which is used to implement the IEEE Std

1149.1™ boundary scan protocol.

CLKCTRL

Clock control

module

Clocks

The clock control module, or CLKCTRL, generates the clock domains for all

components in the i.MX28 system. The crystal clock or PLL clock are the two

fundamental sources used to produce most of the clock domains. For lower

performance and reduced power consumption, the crystal clock is selected.

The PLL is selected for higher performance requirements but requires

increased power consumption. In most cases, when the PLL is used as the

source, a Phase Fractional Divider (PFD) can be programmed to reduce the

PLL clock frequency by up to a factor of 2.

DCP

Data

co-processor

Security

This module provides support for general encryption and hashing functions

typically used for security functions. Because its basic job is moving data

from memory to memory, it also incorporates a memory-copy (memcopy)

function for both debugging and as a more efficient method of copying data

between memory blocks than the DMA-based approach.

IMX28AEC Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc

IMX28AEC Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc

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