V62SLASH12615-01XE-R datasheet(3/92 Pages) TI1

3 / 92 page

DP83848-EP

www.ti.com

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

4.1.4

Auto-Negotiation Restart

...................................................................................... 38

4.1.5

Enabling Auto-Negotiation via Software

..................................................................... 39

4.1.6

Auto-Negotiation Complete Time

............................................................................. 39

4.2

Auto-MDIX

.................................................................................................................. 39

4.3

PHY Address

............................................................................................................... 39

4.3.1

MII Isolate Mode

................................................................................................ 40

4.4

LED Interface

.............................................................................................................. 40

4.4.1

LEDs

............................................................................................................. 41

4.4.2

LED Direct Control

............................................................................................. 42

4.5

Half Duplex vs Full Duplex

............................................................................................... 42

4.6

Internal Loopback

......................................................................................................... 42

4.7

BIST

......................................................................................................................... 43

FUNCTIONAL DESCRIPTION

............................................................................................... 44

5.1

MII Interface

................................................................................................................ 44

5.1.1

Nibble-Wide MII Data Interface

............................................................................... 44

5.1.2

Collision Detect

................................................................................................. 44

5.1.3

Carrier Sense

................................................................................................... 45

5.2

Reduced MII Interface

.................................................................................................... 45

5.3

10 Mb Serial Network Interface (SNI)

.................................................................................. 46

5.4

802.3u MII Serial Management Interface

............................................................................... 46

5.4.1

Serial Management Register Access

........................................................................ 46

5.4.2

Serial Management Access Protocol

........................................................................ 46

5.4.3

Serial Management Preamble Suppression

................................................................ 47

ARCHITECTURE

................................................................................................................ 48

6.1

100BASE-TX Transmitter

................................................................................................ 48

6.1.1

Code-Group Encoding and Injection

......................................................................... 49

6.1.2

Scrambler

........................................................................................................ 50

6.1.3

NRZ to NRZI Encoder

.......................................................................................... 50

6.1.4

Binary to MLT-3 Convertor

.................................................................................... 50

6.2

100BASE-TX Receiver

................................................................................................... 50

6.2.1

Analog Front End

............................................................................................... 51

6.2.2

Digital Signal Processor

....................................................................................... 51

6.2.2.1

Digital Adaptive Equalization and Gain Control

................................................ 52

6.2.2.2

Base Line Wander Compensation

............................................................... 53

6.2.3

Signal Detect

.................................................................................................... 53

6.2.4

MLT-3 to NRZI Decoder

....................................................................................... 53

6.2.5

NRZI to NRZ

.................................................................................................... 53

6.2.6

Serial to Parallel

................................................................................................ 54

6.2.7

Descrambler

..................................................................................................... 54

6.2.8

Code-Group Alignment

........................................................................................ 54

6.2.9

4B/5B Decoder

.................................................................................................. 54

6.2.10

100BASE-TX Link Integrity Monitor

.......................................................................... 54

6.2.11

Bad SSD Detection

............................................................................................. 55

6.3

10BASE-T Transceiver Module

.......................................................................................... 55

6.3.1

Operational Modes

............................................................................................. 55

6.3.1.1

Half Duplex Mode

.................................................................................. 55

6.3.1.2

Full Duplex Mode

.................................................................................. 55

6.3.2

Smart Squelch

.................................................................................................. 55

6.3.3

Collision Detection and SQE

.................................................................................. 56

6.3.4

Carrier Sense

................................................................................................... 56

6.3.5

Normal Link Pulse Detection/Generation

.................................................................... 56

6.3.6

Jabber Function

................................................................................................. 56

6.3.7

Automatic Link Polarity Detection and Correction

.......................................................... 57

Contents

V62/12615-01XE-R Datasheet(PDF) 3 Page - Texas Instruments

V62/12615-01XE-R Datasheet(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL