V62SLASH12615-01XE-R datasheet(74/92 Pages) TI1

74 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

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9.2.9

Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its link partner during auto-

negotiation.

Table 9-11. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x07

BIT

BIT NAME

DEFAULT

DESCRIPTION

Next Page Indication:

0, RW

0 = No other Next Page Transfer desired

1 = Another Next Page desired

RESERVED

0, RO

RESERVED: Writes ignored, read as 0

Message Page:

1, RW

1 = Message Page

0 = Unformatted Page

Acknowledge2:

1 = Will comply with message

ACK2

0, RW

0 = Cannot comply with message

Acknowledge2 is used by the next page function to indicate that Local

Device has the ability to comply with the message received.

Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word was 0

0 = Value of toggle bit in previously transmitted Link Code Word was 1

TOG_TX

0, RO

Toggle is used by the Arbitration function within Auto-Negotiation to

ensure synchronization with the Link Partner during Next Page

exchange. This bit shall always take the opposite value of the Toggle

bit in the previously exchanged Link Code Word.

This field represents the code field of the next page transmission. If the

MP bit is set (bit 13 of this register), then the code shall be interpreted

as a "Message Page”, as defined in annex 28C of IEEE 802.3u.

Otherwise, the code shall be interpreted as an "Unformatted Page”, and

10:0

CODE

<000 0000 0001>, RW

the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in

Annex 28C of IEEE 802.3u.

9.3

Extended Registers

9.3.1

PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed

information.

Table 9-12. PHY Status Register (PHYSTS), Address 0x10

BIT

BIT NAME

DEFAULT

DESCRIPTION

RESERVED

0, RO

RESERVED: Write ignored, read as 0

MDI-X mode as reported by the Auto-Negotiation logic:

This bit will be affected by the settings of the MDIX_EN and

FORCE_MDIX bits in the PHYCR register. When MDIX is enabled,

but not forced, this bit will update dynamically as the Auto-MDIX

algorithm swaps between MDI and MDI-X configurations.

MDI-X Mode

0, RO

1 = MDI pairs swapped

(Receive on TPTD pair, Transmit on TPRD pair)

0 = MDI pairs normal

(Receive on TRD pair, Transmit on TPTD pair)

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