V62SLASH12615-01XE-R datasheet(76/92 Pages) TI1

76 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

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Table 9-12. PHY Status Register (PHYSTS), Address 0x10 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

Duplex:

This bit indicates duplex status and is determined from Auto-

Negotiation or Forced Modes.

1 = Full duplex mode

Duplex Status

0, RO

0 = Half duplex mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete

and there is a valid link or if Auto-Negotiation is disabled and there is

a valid link.

Speed10:

This bit indicates the status of the speed and is determined from Auto-

Negotiation or Forced Modes.

1 = 10 Mb/s mode

Speed Status

0, RO

0 = 100 Mb/s mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete

and there is a valid link or if Auto-Negotiation is disabled and there is

a valid link.

Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register,

except that it will not be cleared upon a read of the PHYSTS register.

Link Status

0, RO

1 = Valid link established (for either 10 or 100 Mb/s operation)

0 = Link not established

9.3.2

MII Interrupt Control Register (MICR)

This register implements the MII interrupt PHY specific control register. Sources for interrupt generation

include: energy detect state change, link state change, speed status change, duplex status change, auto-

negotiation complete or any of the counters becoming half-full. The individual interrupt events must be

enabled by setting bits in the MII interrupt status and event control register (MISR).

Table 9-13. MII Interrupt Control Register (MICR), Address 0x11

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:3

RESERVED

0, RO

Reserved: Write ignored, Read as 0

Test Interrupt:

Forces the PHY to generate an interrupt to facilitate interrupt testing.

Interrupts will continue to be generated as long as this bit remains set.

TINT

0, RW

1 = Generate an interrupt

0 = Do not generate interrupt

Interrupt Enable:

Enable interrupt dependent on the event enables in the MISR register.

INTEN

0, RW

1 = Enable event based interrupts

0 = Disable event based interrupts

Interrupt Output Enable:

Enable interrupt events to signal via the PWR_DOWN/INT pin by

configuring the PWR_DOWN/INT pin as an output.

INT_OE

0, RW

1 = PWR_DOWN/INT is an Interrupt Output

0 = PWR_DOWN/INT is a Power Down Input

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