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V62/12615-01XE-R Datasheet(PDF) 75 Page - Texas Instruments |
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V62/12615-01XE-R Datasheet(HTML) 75 Page - Texas Instruments |
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75 / 92 page ![]() DP83848-EP www.ti.com SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013 Table 9-12. PHY Status Register (PHYSTS), Address 0x10 (continued) BIT BIT NAME DEFAULT DESCRIPTION Receive Error Latch: This bit will be cleared upon a read of the RECR register. 13 Receive Error Latch 0, RO/LH 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0) 0 = No receive error event has occurred Polarity Status: This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read of the 10BTSCR register, but not upon a read 12 Polarity Status 0, RO of the PHYSTS register. 1 = Inverted Polarity detected 0 = Correct Polarity detected False Carrier Sense Latch: This bit will be cleared upon a read of the FCSR register. False Carrier Sense 11 0, RO/LH 1 = False Carrier event has occurred since last read of FCSCR Latch (address 0x14) 0 = No False Carrier event has occurred 10 Signal Detect 0, RO/LL 100Base-TX unconditional Signal Detect from PMD 9 Descrambler Lock 0, RO/LL 100Base-TX Descrambler Lock from PMD Link Code Word Page Received: This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a read of the PHYSTS register. 8 Page Received 0, RO 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address 0x06, bit 1) 0 = Link Code Word Page has not been received MII Interrupt Pending: 1 = Indicates that an internal interrupt is pending. Interrupt source can 7 MII Interrupt 0, RO be determined by reading the MISR Register (0x12h). Reading the MISR will clear the Interrupt. 0= No interrupt pending Remote Fault: 1 = Remote Fault condition detected (cleared on read of BMSR 6 Remote Fault 0, RO (address 01h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. 0 = No remote fault condition detected Jabber Detect: This bit only has meaning in 10 Mb/s mode This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register. 5 Jabber Detect 0, RO 1 = Jabber condition detected 0 = No Jabber Auto-Negotiation Complete: 4 Auto-Neg Complete 0, RO 1 = Auto-Negotiation complete 0 = Auto-Negotiation not complete Loopback: 3 Loopback Status 0, RO 1 = Loopback enabled 0 = Normal operation Copyright © 2012–2013, Texas Instruments Incorporated REGISTER BLOCK 75 Submit Documentation Feedback Product Folder Links: DP83848-EP |
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