V62SLASH12615-01XE-R datasheet(40/92 Pages) TI1

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VCC

PHYAD0 = 1

PHYAD1 = 1

PHYAD2 = 0

PHYAD3 = 0

PHYAD4 = 0

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

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The DP83848 can be set to respond to any of 32 possible PHY addresses via strap pins. The information

is latched into the PHYCR (address 19h, bits [4:0]) at device power-up and hardware reset. The PHY

address pins are shared with the RXD and COL pins. Each DP83848 or port sharing an MDIO bus in a

system must have a unique physical address.

The DP83848 supports PHY address strapping values 0 (<00000>) through 31 (<11111>). Strapping PHY

address 0 puts the part into isolate mode. It should also be noted that selecting PHY address 0 via an

MDIO write to PHYCR will not put the device in isolate mode.

For further detail relating to the latch-in timing requirements of the PHY address pins, as well as the other

hardware configuration pins, refer to the Reset summary in Section 8.

Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pull-

down resistors, the default setting for the PHY address is 00001 (01h).

Refer to Figure 4-1 for an example of a PHYAD connection to external components. In this example, the

PHYAD strapping results in address 00011 (03h).

Figure 4-1. PHYAD Strapping Example

4.3.1

MII Isolate Mode

The DP83848 can be put into MII isolate mode by writing to bit 10 of the BMCR register or by strapping in

physical address 0. It should be noted that selecting physical address 0 via an MDIO write to PHYCR will

not put the device in the MII isolate mode.

When in the MII isolate mode, the DP83848 does not respond to packet data present at TXD[3:0], TX_EN

inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and

CRS outputs. When in Isolate mode, the DP83848 will continue to respond to all management

transactions.

While in Isolate mode, the PMD output pair will not transmit packet data but will continue to source

100BASE-TX scrambled idles or 10BASE-T normal link pulses.

The DP83848 can auto-negotiate or parallel detect to a specific technology depending on the receive

signal at the PMD input pair. A valid link can be established for the receiver even when the DP83848 is in

Isolate mode.

4.4

LED Interface

The DP83848 supports three configurable light emitting diode (LED) pins. The device supports three LED

configurations: Link, Speed, Activity and Collision. Functions are multiplexed among the LEDs. The

PHYCR for the LEDs can also be selected through address 19h, bits [6:5].

CONFIGURATION

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V62/12615-01XE-R Datasheet(PDF) 40 Page - Texas Instruments

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