V62SLASH12615-01XE-R datasheet(46/92 Pages) TI1

46 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

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5.3

10 Mb Serial Network Interface (SNI)

The DP83848 incorporates a 10 Mb serial network interface (SNI) which allows a simple serial data

interface for 10 Mb only devices. This is also referred to as a 7-wire interface. While there is no defined

standard for this interface, it is based on early 10 Mb physical layer devices. Data is clocked serially at

10 MHz using separate transmit and receive paths. The following pins are used in SNI mode:

•

TX_CLK

•

TX_EN

•

TXD[0]

•

RX_CLK

•

RXD[0]

•

CRS

•

COL

5.4

802.3u MII Serial Management Interface

5.4.1

Serial Management Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that

are accessible through the management interface pins MDC and MDIO. The DP83848 implements all the

required MII registers as well as several optional registers. A description of the serial management access

protocol follows.

5.4.2

Serial Management Access Protocol

The serial control interface consists of two pins, management data clock (MDC) and management data

input/output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is

bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in

Table 5-2.

The MDIO pin requires a pull-up resistor (1.5 k

Ω) which, during IDLE and turnaround, will pull MDIO high.

In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous

logic ones on MDIO to provide the DP83848 with a sequence that can be used to establish

synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC

clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time

32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device

if an invalid start, opcode, or turnaround bit is detected.

The DP83848 waits until it has received this preamble sequence before responding to any other

transaction. Once the DP83848 serial management port has been initialized no further preamble

sequencing is required until after a power-on/reset, invalid start, invalid opcode, or invalid turnaround bit

has occurred.

The start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle

line state.

Turnaround is defined as an idle bit time inserted between the register address field and the data field. To

avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first

bit of turnaround. The addressed DP83848 drives the MDIO with a zero for the second bit of turnaround

and follows this with the required data. Figure 5-1 shows the timing relationship between MDC and the

MDIO as driven or received by the station (STA) and the DP83848 (PHY) for a typical register read

access.

For write transactions, the station management entity writes data to the addressed DP83848 thus

eliminating the requirement for MDIO turnaround. The turnaround time is filled by the management entity

by inserting <10>. Figure 5-2 shows the timing relationship for a typical MII register write access.

FUNCTIONAL DESCRIPTION

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