V62SLASH12615-01XE-R datasheet(83/92 Pages) TI1

83 / 92 page

DP83848-EP

www.ti.com

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

9.3.11 CD Test and BIST Extensions Register (CDCTRL1)

Table 9-22. CD Test and BIST Extensions Register (CDCTRL1), Address 0x1B

BIT

BIT NAME

DEFAULT

DESCRIPTION

BIST ERROR Counter:

BIST_ERROR_CO

Counts number of errored data nibbles during Packet BIST. This value

15:8

0, RO

UNT

will reset when Packet BIST is restarted. The counter sticks when it

reaches its max count.

7:6

RESERVED

0, RW

RESERVED: Must be zero

Packet BIST Continuous Mode:

Allows continuous pseudo random data transmission without any

break in transmission. This can be used for transmit VOD testing. This

BIST_CONT_MOD E

0, RW

is used in conjunction with the BIST controls in the PHYCR Register

(0x19h). For 10Mb operation, jabber function must be disabled, bit 0

of the 10BTSCR (0x1Ah), JABBER_DIS = 1.

CD Pattern Enable for 10Mb:

CDPATTEN_10

0, RW

1 = Enabled

0 = Disabled

RESERVED

0, RW

RESERVED: Must be zero

Defines gap between data or NLP test sequences:

10MEG_PATT_GA P

0, RW

1 = 15

μs

0 = 10

μs

CD Pattern Select[1:0]:

If CDPATTEN_10 = 1:

00 = Data, EOP0 sequence

1:0

CDPATTSEL[1:0]

00, RW

01 = Data, EOP1 sequence

10 = NLPs

11 = Constant Manchester 1s (10MHz sine wave) for harmonic

distortion testing

9.3.12 Energy Detect Control (EDCR)

Table 9-23. Energy Detect Control (EDCR), Address 0x1D

BIT

BIT NAME

DEFAULT

DESCRIPTION

Energy Detect Enable:

Allow Energy Detect Mode.

ED_EN

0, RW

When Energy Detect is enabled and Auto-Negotiation is disabled via

the BMCR register, Auto-MDIX should be disabled via the PHYCR

Energy Detect Automatic Power Up:

Automatically begin power up sequence when Energy Detect Data

ED_AUTO_UP

1, RW

Threshold value (EDCR[3:0]) is reached. Alternatively, device could

be powered up manually using the ED_MAN bit (ECDR[12]).

Energy Detect Automatic Power Down:

Automatically begin power down sequence when no energy is

ED_AUTO_DOWN

1, RW

detected. Alternatively, device could be powered down using the

ED_MAN bit (EDCR[12]).

Energy Detect Manual Power Up/Down:

Begin power up/down sequence when this bit is asserted. When set,

the Energy Detect algorithm will initiate a change of Energy Detect

ED_MAN

0, RW/SC

state regardless of threshold (error or data) and timer values. In

managed applications, this bit can be set after clearing the Energy

Detect interrupt to control the timing of changing the power state.

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