V62SLASH12615-01XE-R datasheet(57/92 Pages) TI1

57 / 92 page

DP83848-EP

www.ti.com

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

Once disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC

module's internal transmit enable is asserted. This signal has to be deasserted for approximately 500 ms

(the “unjab” time) before the Jabber function re-enables the transmit outputs.

The Jabber function is only relevant in 10BASE-T mode.

6.3.7

Automatic Link Polarity Detection and Correction

The DP83848's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit.

When three consecutive inverted link pulses are received, bad polarity is reported.

A polarity reversal can be caused by a wiring error at either end of the cable, usually at the main

distribution frame (MDF) or patch panel in the wiring closet.

The bad polarity condition is latched in the 10BTSCR register. The DP83848's 10BASE-T transceiver

module corrects for this error internally and will continue to decode received data correctly. This eliminates

the need to correct the wiring error immediately.

6.3.8

Transmit and Receive Filtering

External 10BASE-T filters are not required when using the DP83848, as the required signal conditioning is

integrated into the device.

Only isolation transformers and impedance matching resistors are required for the 10BASE-T transmit and

receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are

attenuated by at least 30 dB.

6.3.9

Transmitter

The encoder begins operation when the transmit enable input (TX_EN) goes high and converts NRZ data

to preemphasized Manchester data for the transceiver. For the duration of TX_EN, the serialized transmit

data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD must be valid on the rising

edge of transmit clock (TX_CLK). Transmission ends when TX_EN deasserts. The last transition is always

positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the last bit

is a zero.

6.3.10 Receiver

The decoder detects the end of a frame when no additional mid-bit transitions are detected. Within one

and a half bit times after the last bit, carrier sense is de-asserted. Receive clock stays active for five more

bit times after CRS goes low, to guarantee the receive timings of the controller.

ARCHITECTURE

Submit Documentation Feedback

Product Folder Links: DP83848-EP

V62/12615-01XE-R Datasheet(PDF) 57 Page - Texas Instruments