V62SLASH12615-01XE-R datasheet(4/92 Pages) TI1

4 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

www.ti.com

6.3.8

Transmit and Receive Filtering

............................................................................... 57

6.3.9

Transmitter

...................................................................................................... 57

6.3.10

Receiver

......................................................................................................... 57

DESIGN GUIDELINES

......................................................................................................... 58

7.1

TPI Network Circuit

........................................................................................................ 58

7.2

ESD Protection

............................................................................................................ 58

7.3

Clock In (X1) Requirements

.............................................................................................. 58

7.3.1

Oscillator

......................................................................................................... 58

7.3.2

Crystal

............................................................................................................ 59

7.4

Power Feedback Circuit

.................................................................................................. 60

7.5

Power Down and Interrupt

............................................................................................... 60

7.5.1

Power Down Control Mode

.................................................................................... 60

7.5.2

Interrupt Mechanisms

.......................................................................................... 60

7.6

Energy Detect Mode

...................................................................................................... 61

7.7

Thermal Vias Recommendation

......................................................................................... 61

RESET OPERATION

........................................................................................................... 63

8.1

Hardware Reset

........................................................................................................... 63

8.2

Software Reset

............................................................................................................ 63

............................................................................................................. 64

9.1

................................................................................................................................ 64

9.2

......................................................................................................... 68

9.2.1

Basic Mode Control Register (BMCR)

....................................................................... 68

9.2.2

Basic Mode Status Register (BMSR)

........................................................................ 69

9.2.3

PHY Identifier Register #1 (PHYIDR1)

...................................................................... 70

9.2.4

PHY Identifier Register #2 (PHYIDR2)

...................................................................... 70

9.2.5

Auto-Negotiation Advertisement Register (ANAR)

......................................................... 71

9.2.6

Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

............................... 72

9.2.7

Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)

................................. 72

9.2.8

Auto-Negotiate Expansion Register (ANER)

................................................................ 73

9.2.9

Auto-Negotiation Next Page Transmit Register (ANNPTR)

............................................... 74

9.3

Extended Registers

....................................................................................................... 74

9.3.1

PHY Status Register (PHYSTS)

.............................................................................. 74

9.3.2

MII Interrupt Control Register (MICR)

........................................................................ 76

9.3.3

MII Interrupt Status and Miscellaneous Control Register (MISR)

........................................ 77

9.3.4

False Carrier Sense Counter Register (FCSCR)

........................................................... 78

9.3.5

Receiver Error Counter Register (RECR)

................................................................... 78

9.3.6

100 Mb/s PCS Configuration and Status Register (PCSR)

............................................... 78

9.3.7

RMII and Bypass Register (RBR)

............................................................................ 79

9.3.8

LED Direct Control Register (LEDCR)

....................................................................... 80

9.3.9

PHY Control Register (PHYCR)

.............................................................................. 80

9.3.10

10Base-T Status/Control Register (10BTSCR)

............................................................. 82

9.3.11

CD Test and BIST Extensions Register (CDCTRL1)

...................................................... 83

9.3.12

Energy Detect Control (EDCR)

............................................................................... 83

Contents

V62/12615-01XE-R Datasheet(PDF) 4 Page - Texas Instruments

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