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V62/12615-01XE-R Datasheet(PDF) 54 Page - Texas Instruments

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Part # V62/12615-01XE-R
Description  PHYTER MILITARY TEMPERATURE SINGLE PORT 10/100 MB/S ETHERNET PHYSICAL LAYER TRANSCEIVER
PDF  92 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

V62/12615-01XE-R Datasheet(HTML) 54 Page - Texas Instruments

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DP83848-EP
SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013
www.ti.com
6.2.6
Serial to Parallel
The 100BASE-TX receiver includes a serial to parallel converter which supplies 5-bit wide data symbols to
the PCS Rx state machine.
6.2.7
Descrambler
A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an
identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the
scrambled data (SD) as represented in the equations:
SD = (UD
⊕ N)
(1)
UD = (SD
⊕ N)
(2)
Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the
knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the
descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group
in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and
generate unscrambled data in the form of unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must continuously monitor the validity of the
unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to
constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer
starts a 722
μs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722 μs
period, the hold timer will reset and begin a new countdown. This monitoring operation will continue
indefinitely given a properly operating network connection with good signal integrity. If the line state
monitor does not recognize sufficient unscrambled IDLE code-groups within the 722
μs period, the entire
descrambler will be forced out of the current state of synchronization and reset in order to reacquire
synchronization.
6.2.8
Code-Group Alignment
The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the
descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5
bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group
pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.
6.2.9
4B/5B Decoder
The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B
nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and
replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble
pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the
duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair
denoting the end of stream delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.
6.2.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the
transmit and receive PCS layer.
Signal detect must be valid for 395 µs to allow the link monitor to enter the link up state, and enable the
transmit and receive functions.
54
ARCHITECTURE
Copyright © 2012–2013, Texas Instruments Incorporated
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