RM0352 datasheet(93/138 Pages) STMICROELECTRONICS

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RM0352

I2C bus interface

137

Description:

The I2CMISR register indicates the interrupt sources after masking. For the

description of each single bit, refer to the register I2C_RISR. The output signal

int_gbl is asserted when at least one interrupt source of this register is

pending.

10.2.13

I2C interrupt clear register (I2C_ICR)

Table 83. I2C interrupt clear register (I2C_ICR)

Address:

I2CBaseAddress + 0x38

Type:

Reset:

0x00000000

Description:

The I2C_ICR register indicates the interrupt sources after masking. For the

description of each single bit, refer to the register I2C_RISR. When writing to

this register, each data bit that is set to 1b causes the corresponding bit in the

status registers to be cleared. Data bits that are set to 0b have no effect on the

corresponding bit in the register.

10.2.14

I2C hold time data (I2C_THDDAT)

Table 84. I2C hold time data (I2C_THDDAT)

Address:

I2CBaseAddress + 0x04C

Type:

Reset:

0x00000014

Description:

The I2C_THDDAT register is an 8-bit registers, that controls the hold time data

for F/S mode. The register is read-write.

I2C interrupt clear register (I2C_ICR)

27 26

22 21

14 13 12 11 10

RESERVED

I2C hold time data (I2C_THDDAT)

30 29 28

23 22

18 17 16

13 12 11 10

RESERVED

I2C_THDDAT

RRW

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