AT697F_14 datasheet(69/176 Pages) ATMEL

69 / 176 page

AT697F

7703E–AERO–08/11

The time tag counter is stored in the trace as an execution time reference.

Trace Buffer

The trace buffer consists in a circular buffer that stores the executed instructions and/or

the internal bus data transfers. The size of the trace buffer is 512 lines of 16 bytes. The

trace buffer operation is controlled through the DSU control register (DSUC) and the

trace buffer control register (TBCTL). When the processor enters debug mode, tracing is

suspended.

The trace buffer can contain the executed instructions, the transfers on the internal bus

or both (mixed-mode). The trace buffer control register (TBCTL) contains an instruction

trace index counter (TBCTL.icnt) and an internal bus trace index counter

(TBCTL.bcnt) that store the address of the trace buffer location that will be written on

next trace. Since the buffer is circular, they actually point to the oldest entry in the buffer.

The index counters are automatically incremented after each stored trace entry.

The trace buffer operation is controlled as follows:

•

Tracing can be globally enabled/disabled (DSUC.te)

•

Instruction tracing can be enabled/disabled (TBCTL.ti)

•

Internal bus tracing can be enabled/disabled (TBCTL.ta)

•

Internal bus trace freeze on entry into debug mode can be enabled/disabled

(TBCTL.af)

Instruction trace

When instruction tracing is enabled (TBCTL.ti = 1), one instruction is stored per line in

the trace buffer with the exception of multi-cycle instructions. Multi-cycle instructions can

be entered two or three times in the trace buffer:

•

For store instructions, bits [95:64] correspond to the store address on the first entry

and to the stored data on the second entry (and third in case of STD). Bit 126 is set

logical one on the second and third entry to indicate this.

•

A double load (LDD) is entered twice in the trace buffer, with bits [95:64] containing

the loaded data.

•

Multiply and divide instructions are entered twice, but only the last entry contains the

result. Bit 126 is set for the second entry.

•

For FPU operation producing a double-precision result, the first entry contains the

most-significant 32 bits of the results in bits [63:32] while the second entry contains

the least-significant 32 bits in bits [63:32].

AT697F Datasheet(PDF) 69 Page - ATMEL Corporation

AT697F Datasheet(HTML) 69 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL