AT697F_14 datasheet(6/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

These active low outputs provide the chip select signals for decoding two SDRAM

banks.

SDRAS*- SDRAM row address strobe (output)

This active low output provides the RAS signal (Row Access Strobe) for SDRAM

devices.

SDCAS* - SDRAM column address strobe (output)

This active low output provides the CAS signal (Column Access Strobe) for SDRAM

devices.

SDWE* - SDRAM write strobe (output)

This active low output provides the write strobe for SDRAM devices.

SDDQM[3:0] - SDRAM data mask (output)

These active high outputs provide the DQM strobe (Data Mask) for SDRAM devices.

General-Purpose Interface

PIO[15:0] - Parallel I/O port (bi-directional)

These bi-directional signals can be used as general-purpose inputs or outputs to control

external devices. Some of these signals have an alternate function and also serve as

inputs or outputs for internal peripherals.

PCI interface

System

PCI_CLK - PCI clock (input)

This signal provides timing for all transactions on the PCI bus. All other PCI signals,

except PCI_RST*, are sampled on the rising edge of PCI_CLK and all other timing

parameters are defined with respect to this edge.

PCI_RST* - PCI Reset (input)

This active low input is used to bring PCI-specific registers, sequencers and signals to a

consistent state. When asserted, it immediately halts and resets the PCI interface. The

PCI interface resumes execution after the 5th rising edge of the PCI clock after

PCI_RST* was de-asserted.

SYSEN* - System Enable (input)

This active low input is used to configure the PCI interface as the Host-Bridge for the

PCI bus (also called the System-Controller in a CompactPCI-compliant environment). If

de-asserted, the PCI interface is configured as a satellite on the PCI bus.

Caution: This signal shall be kept static and free from glitches while the processor is operating, as

it is not sampled internally. Changing the signal shall only be performed while the proces-

sor is under reset otherwise the processor's behavior is not predictable.

Address & Data

A/D[31:0] - PCI Address Data (bi-directional)

Address and Data are multiplexed on the same PCI pins. During the address phase,

A/D[31:0] contain a physical address (32 bits). For I/O, this is a byte address; for con-

figuration and memory, it is a 32-bit address. During data phases, A/D[7:0] contain

the least significant byte and A/D[31:24] contain the most significant byte.

C/BE*[3:0] - PCI Bus Command and Byte Enables (bi-directional)

AT697F Datasheet(PDF) 6 Page - ATMEL Corporation

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