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AT697F Datasheet(PDF) 48 Page - ATMEL Corporation

Part # AT697F
Description  SPARC V8 High Performance Low-power 32-bit Architecture
PDF  176 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT697F Datasheet(HTML) 48 Page - ATMEL Corporation

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AT697F
7703E–AERO–08/11
The protected memory bank is partitioned as follows:
lower 80% of the memory bank available as program or data memory
upper 20% of the memory bank allocated to the EDAC checkbits (a maximum of 4
unusable bytes before the checkbit area)
Accessing the EDAC checkbits is performed as follows:
start address from the topmost byte in the same memory bank (no bank size
information needed)
addrcheckbits = addrbank-top - ((addrdata - addrbank-start) / 4)
checkbits bytes allocated downwards (address bits inversion technique used)
Figure 29. 8-bit EDAC-Protected Memory Organization
data1 byte0
data1 byte1
data1 byte2
data1 byte3
data2 byte0
data2 byte1
data2 byte2
data2 byte3
checksum2
checksum1
Co
rre
spo
nd
ing
Ch
eck
sum
0x00000007
0x00000006
0x00000005
0x00000004
0x00000003
0x00000002
0x00000001
0x00000000
0x0FFFFFFF
0x0FFFFFFE
memory top address
EDAC Testing
Operation of the EDAC can be bypassed for testing purpose and is controlled in a mem-
ory configuration register (MCFG3).
Figure 30. EDAC testing overview
Memory Configuration Reg.
MCFG3
CB[7:0]
8
EDAC
8
8
TCB
TCB
WB
RB
Write Test
When EDAC write bypass is enabled (MCFG3.wb = 1), the test checkbits (MCFG3.tcb)
replace the EDAC generated checkbits during a data store.
Read Test
When EDAC read diagnostic is enabled (MCFG3.rb = 1), the test checkbits
(MCFG3.tcb) are updated(1) with the read checkbits during a data load or an instruction
fetch.
Note:
1. The EDAC test routine shall be executed entirely from the instruction cache (when
activated) or from an area without EDAC activated and different from the one being



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