AT697F_14 datasheet(72/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

Debug Operations

Instruction Breakpoints

To insert instruction breakpoints, the breakpoint instruction (ta 1) should be used. This

will leave the four IU hardware breakpoints free to be used as data watchpoints. Since

cache snooping is only perfomed on the data cache, the instruction cache must be

flushed after the insertion or removal of breakpoints. To minimize the influence on exe-

cution, it is enough to clear the corresponding instruction cache tag (which is accessible

through the DSU).

The DSU hardware breakpoints should only be used to freeze the trace buffer, and not

for software debugging since there is a 4-cycle delay from the breakpoint hit before the

processor enters the debug mode.

Single Stepping

When single-stepping is enabled (TBCTL.ss = 1), clearing the break-now bit

(TBCTL.bn = 0) resumes processor execution for one instruction and then automati-

cally re-enters debug mode.

DSU Trap

The DSU trap register (DTR) consists in a read-only register that indicates which SPARC

trap type caused the processor to enter debug mode.

When debug mode is forced by asserting the break-now bit (TBCTL.bn = 1), a

watchpoint_detected trap (0x0B) is generated.

DSU Communication

Link

DSU communication link consists of a UART connected to the internal bus as a master.

Figure 40. DSU Communication Link Block Diagram

DSURX

DSUTX

Receiver shift register

Transmitter shift register

AHB master interface

AHB data/response

AMBA AHB

Serial port

Controller

8*bitclk

Baud-rate

generator

AMBA APB

A simple communication protocol is supported to transmit access parameters and data.

A link command consist of a control byte, followed by a 32-bit address, followed by

optional write data. If the DSU link response is enabled (DSUC.lr = 1), a response byte

is sent after each read/write access. If disabled, a write access does not return any

response, while a read access only returns the read data.

Data Frame

A DSU data frame consists in a start bit, 8 data bits and a stop bit..

Figure 41. DSU UART Data Frame

Start D0

Stop

Commands

Through the communication link, a read or write transfer can be generated to any

address on the internal bus. A response byte is can optionally be sent when the proces-

sor goes from execution mode to debug mode. Block transfers can be performed be

setting the length field to n-1, where n denotes the number of transferred words. For

write accesses, the control byte and address is sent once, followed by the number of

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