AT697F_14 datasheet(4/176 Pages) ATMEL

4 / 176 page

AT697F

7703E–AERO–08/11

This active low output is asserted when the watchdog timer has expired and remains

asserted until the watchdog timer is reloaded with a non-null value.

BEXC* - Bus exception (input)

This active low input is sampled simultaneously with the data during an access to the

external memory. If asserted, a memory error is generated.

Clock Interface

CLK - Reference clock (input)

This input provides a reference to generate the internal clock used by the processor and

the internal peripherals.

BYPASS - PLL bypass (input with pull-down)

This active high input is used to bypass the internal PLL. When asserted, the processor

is directly clocked from the external reference clock. When de-asserted, the processor

receives its clock from the internal PLL.

Caution: This signal shall be kept static and free from glitches while the processor is operating, as

it is not sampled internally. Changing the signal shall only be performed while the proces-

sor is under reset otherwise the processor's behavior is not predictable.

LOCK - PLL lock (output)

When asserted, this active high output indicates the PLL is locked at a frequency corre-

sponding to four times the frequency of the external reference clock. Caution: this

signal is de-asserted as soon as the PLL unlocks.

SKEW[1:0] - Clock tree skew (input with pull-down)

These input signals are used to programme the skew on the internal triplicated clock

trees.

Caution: These signals shall be kept static and free from glitches while the processor is operating,

as they are not sampled internally. Changing these signals shall only be performed while

the processor is under reset otherwise the processor's behavior is not predictable.

Memory Interface

A[27:0] - Address bus (output)

The lower 28 bits of the 32 bit address bus carry instruction or data addresses during a

fetch or a load/store operation to the external memory. The address of the last external

memory access remains on the address bus whenever the current access can be made

out of the internal cache.

D[31:0] - Data bus (bi-directional)

The 32-bit bi-directional data bus serves as the interface between the processor and the

external memory. The data bus is only driven by the processor during the execution of

integer & floating-point store instructions and the store cycle of atomic-load-store

instructions. It is kept in high impedance otherwise. However:

•only D[31:24] are used during an access to an 8-bit area

•

D[15:0] are used as part of the general-purpose I/O interface whenever all the

memory areas (ROM, SRAM & I/O) are 8-bit wide and the SDRAM interface is not

enabled

CB[7:0] - Check bits (bi-directional)

AT697F Datasheet(PDF) 4 Page - ATMEL Corporation

AT697F Datasheet(HTML) 4 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL