AT697F_14 datasheet(36/176 Pages) ATMEL

36 / 176 page

AT697F

7703E–AERO–08/11

The SRAM interface is controlled in the memory configuration registers (MCFG2 and

MCFG3):

•

interface can be enabled/disabled (MCFG2.si)

•

data bus width can be 8-bit or 32-bit (MCFG2.ramwdh)

•

bank size can be set from 8 KB to 256 MB (MCFG2.rambs)

•

wait-states can be programmed for read access (MCFG2.ramrws) and write access

(MCFG2.ramwws)

•

read-modify-write can be activated for sub-word write operations (MCFG2.ramrmw)

•

EDAC protection(1) can be enabled/disabled (MCFG3.re)

•

read/write access can be BRDY*-controlled (MCFG2.rambrdy)

synchronously/asynchronously(2) (MCFG1.abrdy)

Notes: 1. EDAC protection activation common to SRAM and SDRAM interfaces.

2. Asynchronous BRDY*-control feature common to PROM, SRAM and I/O interfaces.

Figure 14. SRAM Bank Organization

SRAM bank size

256MB

128MB

64MB

Start Address

Memory

assignement

Memory

assignement

Memory

assignement

0x7C000000

Unused

0x78000000

0x74000000

0x70000000

0x6C000000

RAMS*[4]

(1)(2)

RAMS*[4](2)

0x68000000

0x64000000

0x60000000

0x5C000000

RAMS*[1]

RAMS*[3]

Unused

0x58000000

0x54000000

RAMS*[2]

0x50000000

0x4C000000

RAMS*[0]

RAMS*[1]

RAMS*[3]

0x48000000

RAMS*[2]

0x44000000

RAMS*[0]

RAMS*[1]

0x40000000

RAMS*[0]

Notes: 1. When SRAM bank size is set to 256 MB, bank 2 and bank 3 overlap with bank 4.

Because priority is given to bank 4, bank 2 and bank 3 control signals are never

asserted.

2. When SDRAM is enabled, priority is given to the SDRAM over the SRAM. Any mem-

ory access above 0x60000000 is assigned to SDRAM and no SRAM control signal

is asserted.

AT697F Datasheet(PDF) 36 Page - ATMEL Corporation

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