AT697F_14 datasheet(19/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

Operating Modes

Reset Mode

The processor asynchronously enters reset mode as soon as the RESET* signal is

asserted. It synchronously exits reset mode on the 5th rising edge of the SDCLK signal

after the RESET* signal has been deasserted.

While in reset mode, the IU, the FPU and all the peripherals are halted. The processor

disables traps (PSR.et = 0), sets the supervisor mode (PSR.s = 1) and sets the pro-

gram counter to location zero (PC = 0 & nPC = 4). Other IU, FPU and peripheral

registers are initialized as well (see "Register Description").

On exit from reset mode, the processor enters execute mode.

Execute Mode

In execute mode, the processor fetches instructions and executes them in the IU (Inte-

ger Unit) or the FPU (Floating-Point Unit). Please refer to "The SPARC Architecture

Manual - Version 8" for further information.

Error Mode

The processor enters error mode when a synchronous trap must occur while traps are

disabled (PSR.et = 0).

This essentially means that a trap which cannot be ignored occured while another trap is

being serviced. In order for that synchronous trap to be serviced, the processor goes

through the normal operation of a trap, including setting the trap-type bits (TBR.tt) to

identify the trap type. It then enters error mode, halts and asserts the ERROR* signal.

The only way to leave error mode is to assert the RESET* signal, which forces the pro-

cessor into reset mode. All information placed in the IU, FPU and all peripherals

registers from the last execute mode (the trap operation) remains unchanged unless

stated otherwise (see "Register Description"). The code executed upon exit from reset

mode can examine the trap type of the synchronous trap and the IU, FPU and all periph-

erals registers and deal with the information they contain accordingly.

Idle Mode

While in execute mode, the processor may enter idle mode in software.

Entry into idle mode is initiated by writing any value to the idle register (IDLE) and made

effective on the next load instruction(caution). While in idle mode, the IU stops fetching

instructions and is kept into a minimal activity. All other peripherals operate as nominal.

Caution: In order to avoid any unwanted side-effect (idle entry not on the foreseen load instruc-

tion), the load instruction shall immediately follow the write operation to the idle register,

Idle mode is terminated as soon as an unmasked interrupt is pending (ITP.ipend) with

an interrupt number of 15 or greater than the current processor interrupt level

(PSR.pil). Then the processor directly goes through the normal operation of servicing

the interrupt.

Debug Mode

Caution: This section is for information purpose only.

As its name clearly states, the Debug Support Unit (DSU) is exclusively meant for debug-

ging purpose. None of the DSU features shall ever be used in the final application where

the DSU shall be turned into an inactive state (DSUEN, DSUBRE and DSURX tied to a per-

manent low level).

As a special case when the DSU is enabled (DSUEN signal asserted), debug mode is

entered when specific conditions are met (see "Debug Support Unit" and "Register

Description" chapters later in this document).

AT697F Datasheet(PDF) 19 Page - ATMEL Corporation

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