AT697F_14 datasheet(29/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

sponding cache line is invalidated in the data cache if present. Cache snooping has no

overhead and does not affect performance.

Error Reporting

If a memory access error occurs during a data load, the corresponding valid bit in the

cache tag is set and a data_access_error trap (0x09) is generated.

Since the processor executes in parallel with the write buffer, a write error may not

cause an exception to the store instruction. Depending on memory and cache activity,

the external memory write access may not occur until several clock cycles after the

store instructions has completed. If a write error occurs, the currently executing instruc-

tion will take a write_error trap (0x2B).

Caution: The write_error trap handler shall flush the data cache since a write hit would update

the cache while the memory would keep the old value due the write error.

Diagnostic Cache

Access

Tags and data in the instruction and data cache can be accessed through ASI address

space by executing LDA and STA instructions (only the least-significant nibble of the

ASI field -- ASI[3:0] -- is used for mapping to the alternate address space). Address

bits making up the cache offset are used to index the tag to be accessed while the least

significant bits of the bits making up the address tag are used to index the cache set.

The following table summarizes the ASI allocation on the AT697F.

Table 8. ASI Usage

0x0, 0x1, 0x2, 0x3

Force cache miss (replace if cacheable)

0x4, 0x7

Force cache miss (update on hit)

0x5

Flush instruction cache

0x6

Flush data cache

0x8

User instruction (replace if cacheable)

0x9

Supervisor instruction (replace if cacheable)

0xA

User data (replace if cacheable)

0xB

Supervisor data (replace if cacheable)

0xC

Instruction cache tags

0xD

Instruction cache data

0xE

Data cache tags

0xF

Data cache data

Note:

Please refer to "The SPARC Architecture Manual Version 8" document for detailed infor-

mation on ASI usage.

The tags can be directly read/written by executing an LDA/STA instruction with ASI=0xC

for instruction cache tags and ASI=0xE for data cache tags. The cache line and the

cache set are indexed by the address bits making up the cache offset and the least sig-

nificant bits of the address bits making up the address tag..

Similarly, the data sub-blocks are read/written by executing an LDA/STA instruction with

ASI=0xD for instruction cache data and ASI=0xF for data cache data..

Note:

Diagnostic cache access is not possible during a cache flush operation and will cause a

data_exception trap (0x09) if attempted.

ASI

Usage

AT697F Datasheet(PDF) 29 Page - ATMEL Corporation

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