AT697F_14 datasheet(53/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

Internal Clock

When configured for internal clock (UACn.ec = 0), the UART baud-rate comes from a

programmable 12-bits scaler controlled by a configuration register (UASCAn):

•

the scaler is enabled only when the UART transmitter (UACn.te = 0) and/or the

UART receiver (UACn.re = 0) are enabled

•

when enabled (UACn.te = 1 and/or UACn.re = 1), the scaler counter is clocked by

the system clock and decremented on each clock cycle

•

the scaler counter is reloaded from the scaler reload register (UASCAn.rv) after it

underflows and a UART tick is generated for the transmitter and the receiver (tick

frequency is 8 times the desired baud-rate)

The following equations shall be used to calculate the scaler value or the baudrate value

based on the clock frequency:

baudrate =

)

scalerrv

(

sdclkfreq

scalerrv =

baudrate 8

sdclkfreq

variable description:

•

sdclkfreq: internal clock frequency

•

baudrate: targeted/resulting baud rate

•

scalerrv: resulting/targeted scaler reload value

External Clock

When configured for an external clock (UACn.ec = 1), the UART scaler is bypassed

and PIO[3] directly provides the UART tick to the transmitter and the receiver (tick fre-

quency is 8 times the desired baud-rate).

The external clock frequency shall be 8 times the desired baud-rate.

Caution: When configured for an external clock source, the clock high and low time on PIO[3]

shall each be longer than the period of the internal system clock (so proper sampling is

achieved).

Double Buffering

Each UART performs double-buffering (a holding register and a shift register) on the

transmitter and the receiver to optimize the data transfer in both directions (no transmit-

ter stopped waiting for reload, no data loss on receiver overrun).

Hardware Flow-Control

Each UART n can perform hardware flow-control to further optimize and secure data

transfer in both directions:

•

hardware flow-control can be enabled or disabled (UACn.fl)

•

when enabled (UACn.fl = 1) together with the transmitter (UACn.te = 1), no new

data transmit is initiated until the clear-to-send input pin (CTSn) is asserted (data

transmission is not interrupted is deasserted in the middle of the transmission)

•

when enabled (UACn.fl = 1) together with the receiver (UACn.re = 1), the

request-to-send output pin (RTSn) is asserted as long as new data can be received

Noise Filtering

The serial input is shifted through an 8-bit filter which changes output only when all bits

in the filter have the same value, effectively forming a low-pass filter with a cut-off fre-

quency of 1/8 system clock.

AT697F Datasheet(PDF) 53 Page - ATMEL Corporation

AT697F Datasheet(HTML) 53 Page - ATMEL Corporation

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