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AT697F Datasheet(PDF) 74 Page - ATMEL Corporation

Part # AT697F
Description  SPARC V8 High Performance Low-power 32-bit Architecture
PDF  176 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT697F Datasheet(HTML) 74 Page - ATMEL Corporation

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AT697F
7703E–AERO–08/11
JTAG Interface
Overview
The AT697 implements a standard interface compliant with the IEEE 1149.1 JTAG
specification. This interface can be used for PCB testing using the JTAG boundary-scan
capability.
The JTAG interface is accessed through five dedicated pins. In JTAG terminology,
these pins constitute the Test Access Port (TAP).
The following table summarizes the TAP pins and there function at JTAG level.
Table 19. TAP Pins
TCK
Test Clock
Input
Used to clock serial data boundary into scan latches and
control sequence of the test state machine. TCK can be
asynchronous with CLK
TMS
Test Mode select
Input
Primary control signal for the state machine.
Synchronous with TCK. A sequence of values on TMS
adjusts the current state of the TAP.
TDI
Test Data Input
Input
Serial input data to the boundary scan latches.
Synchronous with TCK
TDO
Test Data Output
Output
Serial output data from the boundary scan latches.
Synchronous with TCK
TRST*
Test Reset
Input
Resets the test state machine. can be asynchronous with
TCK
For more details, please refer to the ‘IEEE Standard Test Access Port and Boundary
Scan’ specification.
Any AT697F based system will contain several JTAG compatible chips. These are con-
nected using the minimum (single TMS signal) configuration. This configuration contains
three broadcast signals (TMS, TCK, and TRST*,) which are fed from the JTAG master to
all JTAG slaves in parallel, and a serial path formed by a daisy-chain connection of the
serial test data pins (TDI and TDO) of all slaves.
The TAP supports a BYPASS instruction which places a minimum shift path (1 bit)
between the chip’s TDI and TDO pins. This allows efficient access to any single chip in
the daisy-chain without board-level multiplexing.
Figure 43. JTAG Serial connection using 1 TMS Signal
TDI
TDO
TMS TCK
TRST
TDI
TDO
TMS TCK
TRST
TDI
TDO
TMS TCK
TRST
TDI
TDO
TMS TCK
TRST
TDI
TMS
TCK
TRST
TDO
Part 1
Part 2
Part 3
Part n
Pin
Name
Type
Description



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