AT697F_14 datasheet(33/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

When configured for 8-bit PROM (MCFG1.prwdh = 00), D[31:24] shall be connected

to the memory device(s).

Figure 10. 8-bit PROM Interface

PROM

OE*

AT697

A[27:0]

D[31:24]

A[27:0]

WRITE*

ROMS0*

Since an IU load operation is always performed on a word basis (32-bit), read access to

8-bit memory is transformed into a burst of 4 read access to retrieve the 4 bytes. If

EDAC protection is activated, a 5th byte read access is performed as well to retrieve the

checkbits (see "Error Management - EDAC" section later in this chapter).

During a store operation, only the necessary bytes are written if EDAC protection is not

activated.

Caution: When EDAC protection is activated, only a full word write operation shall be performed (5

bytes).

Memory-Mapped I/O

Overview

The memory controller allows addressing a single memory-mapped I/O area. I/O mem-

ory access control is performed using a dedicated chip select (IOS*) and common

output enable (OE*), read (READ) and write (WRITE*) signals. No EDAC protection is

available in this area.

IOS* decodes a fixed 512 MB(1) area (0x20000000 - 0x3FFFFFFF).

The I/O interface is controlled in the memory configuration registers (MCFG1):

•

interface can be enabled/disabled (MCFG1.ioen)

•

data bus width can be 8-bit or 32-bit (MCFG1.iowdh)(2)

•

wait-states can be programmed for read and write access (MCFG1.iows)

•

read/write access can be BRDY*-controlled (MCFG1.iobrdy)

synchronously/asynchronously(3) (MCFG1.abrdy)

Notes: 1. The upper 256 MB area (0x30000000 - 0x3FFFFFFF) is a shadow of the lower

256 MB area (0x20000000 - 0x2FFFFFFF) because of the 28 bits address bus

limitation.

2. The I/O area shall only be accessed with load/store instructions of a size matching

the configured bus width (LDUB/LDSB/STB when in 8-bit mode and LD/ST when in

32-bit mode).

3. Asynchronous BRDY*-control feature common to PROM, SRAM and I/O interfaces.

Interface Enable

The I/O interface shall be enabled (MCFG1.ioen) before any read or write access is

attempted, otherwise the access is cancelled and:

•an instruction_access_exception trap (0x01) is generated if an instruction

fetch is in progress

•a data_access_exception trap (0x09) is generated if a data load is in progress

•a write_error trap (0x2B) is generated if a data store is in progress

AT697F Datasheet(PDF) 33 Page - ATMEL Corporation

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