V62SLASH13624-01XE-R datasheet(19/77 Pages) TI1

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MSP430F2132-EP

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SLAS913A – JULY 2013 – REVISED AUGUST 2013

Product Folder Links: MSP430F2132-EP

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(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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5.2 THERMAL INFORMATION

THERMAL METRIC(1)

MSP430F2132-EP

UNITS

RHB

32 PINS

θJA

Junction-to-ambient thermal resistance(2)

33.2

°C/W

θJCtop

Junction-to-case (top) thermal resistance(3)

24.3

θJB

Junction-to-board thermal resistance(4)

7.3

ψJT

Junction-to-top characterization parameter(5)

0.3

ψJB

Junction-to-board characterization parameter(6)

7.3

θJCbot

Junction-to-case (bottom) thermal resistance(7)

2.3

(1)

Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(2)

The MSP430F2132 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of

the specified maximum frequency.

5.3 Recommended Operating Conditions

(1)

MIN

NOM

MAX

UNIT

VCC

Supply voltage, AVCC = DVCC = VCC

During program execution

1.8

3.6

During flash memory programming

2.2

3.6

VSS

Supply voltage

AVSS = DVSS = VSS

Operating free-air temperature

I version

-40

°C

Q version

-40

125

fSYSTEM

Processor frequency (maximum MCLK

frequency)(2)(1)

(see Figure 2)

VCC = 1.8 V, Duty cycle = 50% ±10%

MHz

VCC = 2.7 V, Duty cycle = 50% ±10%

VCC ≥ 3.3 V, Duty cycle = 50% ±10%

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