V62SLASH13624-01XE-R datasheet(55/77 Pages) TI1

55 / 77 page

To JTAG

From JTAG

Direction

0: Input

1: Output

P1SEL.x

P1DIR.x

P1IN.x

P1IRQ.x

Module X In

Module X Out

P1OUT.x

Interrupt

Edge Select

Set

P1SEL.x

P1IES.x

P1IFG.x

P1IE.x

DVSS

DVCC

P1REN.x

Pad Logic

Bus

Keeper

P1.5/TA0.0/TMS

P1.6/TA0.1/TCLK

P1.7/TA0.2/TDO/TDI

MSP430F2132-EP

www.ti.com

SLAS913A – JULY 2013 – REVISED AUGUST 2013

Product Folder Links: MSP430F2132-EP

Submit Documentation Feedback

(1)

X = Don't care

(2)

In JTAG mode, the internal pullup or pulldown resistors are disabled.

6.4 Port P1 Pin Schematic: P1.5 to P1.7

Table 19. Port P1 (P1.5 to P1.7) Pin Functions

PIN NAME (P1.x)

FUNCTION

CONTROL BITS AND SIGNALS(1)

P1DIR.x

P1SEL.x

P1SEL2.x=0

JTAG Mode

P1.5/TA0.0/TMS

P1.5 (I/O)

I: 0; O: 1

Timer0_A3.TA0

TMS(2)

P1.6/TA0.1/TDI/TCLK

P1.6 (I/O)

I: 0; O: 1

Timer0_A3.TA1

TDI/TCLK(2)

P1.7/TA0.2/TDO/TDI

P1.6 (I/O)

I: 0; O: 1

Timer0_A3.TA2

TDO/TDI(2)

V62/13624-01XE-R Datasheet(PDF) 55 Page - Texas Instruments

V62/13624-01XE-R Datasheet(HTML) 55 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL