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V62/13624-01XE-R Datasheet(PDF) 54 Page - Texas Instruments |
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V62/13624-01XE-R Datasheet(HTML) 54 Page - Texas Instruments |
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54 / 77 page ![]() To JTAG From JTAG Direction 0: Input 1: Output P1SEL.4 P1DIR.4 P1IN.4 P1IRQ.4 Module X IN SMCLK P1OUT.x Interrupt Edge Select Q EN Set P1SEL.x P1IES.x P1IFG.x P1IE.x DVSS DVCC P1REN.4 Pad Logic 1 1 0 0 1 1 0 Bus Keeper EN P1.4/SMCLK/TCK D EN 54 MSP430F2132-EP SLAS913A – JULY 2013 – REVISED AUGUST 2013 www.ti.com Product Folder Links: MSP430F2132-EP Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated (1) X = Don't care (2) In JTAG mode, the internal pullup or pulldown resistors are disabled. 6.3 Port P1 Pin Schematic: P1.4 Table 18. Port P1 (P1.4) Pin Functions PIN NAME (P1.x) x FUNCTION CONTROL BITS AND SIGNALS(1) P1DIR.x P1SEL.x P1SEL2.x=0 JTAG Mode P1.4/SMCLK/TCK 4 P1.4 (I/O) I: 0; O: 1 0 0 SMCLK 1 1 0 TCK(2) X X 1 |
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