V62SLASH13624-01XE-R datasheet(36/77 Pages) TI1

36 / 77 page

SDA

SCL

1/fSCL

tHD,DAT

tSU,DAT

tHD,STA

tSU,STA tHD,STA

tSU,STO

tSP

MSP430F2132-EP

SLAS913A – JULY 2013 – REVISED AUGUST 2013

www.ti.com

Product Folder Links: MSP430F2132-EP

Submit Documentation Feedback

5.28 USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fUSCI

USCI input clock frequency

Internal: SMCLK, ACLK

External: UCLK

Duty cycle = 50% ± 10%

fSYSTEM

MHz

fSCL

SCL clock frequency

2.2 V, 3 V

400

kHz

tHD,STA

Hold time (repeated) START

fSCL ≤ 100 kHz

2.2 V, 3 V

µs

fSCL > 100 kHz

0.6

tSU,STA

Setup time for a repeated START

fSCL ≤ 100 kHz

2.2 V, 3 V

4.7

µs

fSCL > 100 kHz

0.6

tHD,DAT

Data hold time

2.2 V, 3 V

tSU,DAT

Data setup time

2.2 V, 3 V

250

tSU,STO

Setup time for STOP

2.2 V, 3 V

µs

tSP

Pulse duration of spikes suppressed by input

filter

2.2 V

150

605

3 V

100

605

Figure 8. I2C Mode Timing

V62/13624-01XE-R Datasheet(PDF) 36 Page - Texas Instruments

V62/13624-01XE-R Datasheet(HTML) 36 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL