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V62/13624-01XE-R Datasheet(PDF) 64 Page - Texas Instruments |
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V62/13624-01XE-R Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 77 page ![]() Direction 0: Input 1: Output P3SEL.x P3DIR.x P3IN.x D EN Module X IN Module X OUT P3OUT.x DVSS DVCC Pad Logic 1 1 0 1 0 1 0 P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3REN.x Module direction Bus Keeper EN 64 MSP430F2132-EP SLAS913A – JULY 2013 – REVISED AUGUST 2013 www.ti.com Product Folder Links: MSP430F2132-EP Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated (1) X = Don't care (2) The pin direction is controlled by the USCI module. (3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level. 6.12 Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger Table 27. Port P3 (P3.1 to P3.5) Pin Functions PIN NAME (P3.x) x FUNCTION CONTROL BITS AND SIGNALS(1) P3DIR.x P3SEL.x P3.1/UCB0SIMO/ UCB0SDA 1 P3.1 (I/O) I: 0; O: 1 0 UCB0SIMO/UCB0SDA(2)(3) X 1 P3.2/UCB0SOMI/ UCB0SCL 2 P3.2 (I/O) I: 0; O: 1 0 UCB0SOMI/UCB0SCL(2)(3) X 1 P3.3/UCB0CLK/ UCA0STE 3 P3.3 (I/O) I: 0; O: 1 0 UCB0CLK/UCA0STE(2) X 1 P3.4/UCA0TXD/ UCA0SIMO 4 P3.4 (I/O) I: 0; O: 1 0 UCA0TXD/UCA0SIMO(2) X 1 P3.5/UCA0RXD/ UCA0SOMI 5 P3.5 (I/O) I: 0; O: 1 0 UCA0RXD/UCA0SOMI(2) X 1 |
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