V62SLASH13624-01XE-R datasheet(9/77 Pages) TI1

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MSP430F2132-EP

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SLAS913A – JULY 2013 – REVISED AUGUST 2013

Product Folder Links: MSP430F2132-EP

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(1)

Multiple source flags

(2)

A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or

from within unused address range.

(3)

(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

(4)

Interrupt flags are located in the module.

(5)

In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG

(6)

In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG

(7)

This location is used as bootstrap loader security key (BSLSKEY).

A 0xAA55 at this location disables the BSL completely.

A zero (0x0) disables the erasure of the flash if an invalid password is supplied.

(8)

The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if

necessary.

4.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the

CPU goes into LPM4 immediately after power up.

Table 3. Interrupt Vector Addresses

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

PORIFG

Reset

0xFFFE

31, highest

External reset

RSTIFG

Watchdog

WDTIFG

Flash key violation

KEYV(1)

PC out of range(2)

NMI

NMIIFG

(Non)maskable

0xFFFC

Oscillator fault

OFIFG

(Non)maskable

Flash memory access violation

ACCVIFG(1)(3)

(Non)maskable

Timer1_A2

TA1CCR0 CCIFG(4)

Maskable

0xFFFA

Timer1_A2

TA1CCR1 CCIFG,

Maskable

0xFFF8

TA1CTL TAIFG(1)(4)

Comparator_A+

CAIFG

Maskable

0xFFF6

Watchdog timer

WDTIFG

Maskable

0xFFF4

Timer0_A3

TA0CCR0 CCIFG(4)

Maskable

0xFFF2

Timer0_A3

TA0CCR1 CCIFG,

Maskable

0xFFF0

TA0CCR2 CCIFG,

TA0CTL TAIFG(1)(4)

USCI_A0/USCI_B0 receive

UCA0RXIFG,

UCB0RXIFG(1)(5)

Maskable

0xFFEE

USCI_B0 I2C status

USCI_A0/USCI_B0 transmit

UCA0TXIFG,

UCB0TXIFG(1)(6)

Maskable

0xFFEC

USCI_B0 I2C receive/transmit

ADC10

ADC10IFG(4)

Maskable

0xFFEA

0xFFE8

I/O port P2 (eight flags)

P2IFG.0 to P2IFG.7(1)(4)

Maskable

0xFFE6

I/O port P1 (eight flags)

P1IFG.0 to P1IFG.7(1)(4)

Maskable

0xFFE4

0xFFE2

0xFFE0

See (7)

0xFFDE

See (8)

0xFFDC to 0xFFC0

14 to 0, lowest

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