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TNETV2501INPGF Datasheet(PDF) 154 Page - Texas Instruments |
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TNETV2501INPGF Datasheet(HTML) 154 Page - Texas Instruments |
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154 / 197 page  Electrical Specifications 154 December 2002 − Revised November 2008 SPRS206K 5.7.3 Synchronous DRAM Timings Table 5−13 and Table 5−14 assume testing over recommended operating conditions (see Figure 5−13 through Figure 5−20). Table 5−13. Synchronous DRAM Cycle Timing Requirements NO. MIN MAX UNIT SD6 tsu(EDV-EKO1H) Setup time, read EMIF.Dx valid before ECLKOUT1 high 2 ns SD7 th(EKO1H-EDV) Hold time, read EMIF.Dx valid after ECLKOUT1 high 2 ns Table 5−14. Synchronous DRAM Cycle Switching Characteristics NO. PARAMETER MIN MAX UNIT SD1 td(EKO1H-CEV) Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid 0.8 7 ns SD2 td(EKO1H-BEV) Delay time, ECLKOUT1 high to EMIF.BEx valid 7 ns SD3 td(EKO1H-BEIV) Delay time, ECLKOUT1 high to EMIF.BEx invalid 0.8 ns SD4 td(EKO1H-EAV) Delay time, ECLKOUT1 high to EMIF.Ax valid 7 ns SD5 td(EKO1H-EAIV) Delay time, ECLKOUT1 high to EMIF.Ax invalid 0.8 ns SD8 td(EKO1H-CASV) Delay time, ECLKOUT1 high to EMIF.SDCAS valid 0.8 7 ns SD9 td(EKO1H-EDV) Delay time, ECLKOUT1 high to EMIF.Dx valid 7 ns SD10 td(EKO1H-EDIV) Delay time, ECLKOUT1 high to EMIF.Dx invalid 0.8 ns SD11 td(EKO1H-WEV) Delay time, ECLKOUT1 high to EMIF.SDWE valid 0.8 7 ns SD12 td(EKO1H-RASV) Delay time, ECLKOUT1 high to EMIF.SDRAS valid 0.8 7 ns SD13 td(EKO1H-CKEV) Delay time, ECLKOUT1 high to EMIF.SDCKE valid 0.8 7 ns ECLKOUT1 EMIF.CEx EMIF.BE[3:0] EMIF.A[11:2] EMIF.D[31:0] EMIF.A12 EMIF.AOE/SOE/SDRAS† EMIF.ARE/SADS/ SDCAS/SRE† EMIF.AWE/SWE/SDWE† EMIF.A[21:13] BE1 BE2 BE3 BE4 Bank Column D1 D2 D3 D4 SD8 SD7 SD6 SD5 SD5 SD5 SD1 SD3 SD2 SD8 SD4 SD4 SD4 SD1 READ † EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and EMIF.SDRAS, respectively, during SDRAM accesses. Figure 5−13. SDRAM Read Command (CAS Latency 3) |
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