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TNETV2501INPGF Datasheet(PDF) 84 Page - Texas Instruments |
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TNETV2501INPGF Datasheet(HTML) 84 Page - Texas Instruments |
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84 / 197 page ![]() Functional Overview 84 December 2002 − Revised November 2008 SPRS206K 3.10.5 Auto-Wakeup/Idle Function for McBSP and DMA The 5501 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in power-down mode for the Auto-wakeup/Idle function to work.] 3.10.6 Clock State of Multiplexed Modules The clock to the EMIF module is disabled automatically when this module is not selected through the External Bus Selection Register (XBSR). Note that any accesses to disabled modules will result in a bus error. 3.10.7 IDLE Control and Status Registers The clock domains are controlled by the IDLE Configuration Register (ICR) that allows the user to place different parts of the device in Idle mode. The IDLE Status Register (ISTR) reflects the portion of the device that remains active. The peripheral domain is controlled by the Peripheral IDLE Control Register (PICR). The Peripheral IDLE Status Register (PISTR) reflects the portion of the peripherals that are in the IDLE state. The Master IDLE Control Register (MICR) is used to place the HPI and DMA in Idle mode. The IDLE state of the HPI and DMA is reflected by the Master IDLE Status Register (MISR). The PLL Control/Status Register (PLLCSR) is used to power down the PLL core when the IDLE instruction is executed. The settings in the ICR, PICR, and MICR take effect after the IDLE instruction is executed. For example, writing xxx000001b into the ICR does not indicate that the CPU domain is in IDLE mode; rather, it indicates that after the IDLE instruction, the CPU domain will be in IDLE mode. Procedures for placing portions of the device in Idle mode and taking them out of Idle mode are described in Section 3.10.2 (IDLE Procedures) and Section 3.10.4 (Wake-Up Procedures), respectively. Table 3−26. Clock Domain Memory-Mapped Registers ADDRESS REGISTER NAME 0x0001 IDLE Configuration Register (ICR) 0x0002 IDLE Status Register (ISTR) 0x9400 Peripheral IDLE Control Register (PICR) 0x9401 Peripheral IDLE Status Register (PISTR) 0x9402 Master IDLE Control Register (MICR) 0x9403 Master IDLE Status Register (MISR) |
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