TNETV2501INPGF datasheet(28/197 Pages) TI1

28 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Parallel Port − Control Pins (Continued)

C13

I/O/Z

C, D, E,

The C13 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO33 or external memory interface control signal

EMIF.SOE3. The function of the C13 pin is determined by the state of the GPIO6 pin

during reset. The C13 pin is set to PGPIO33 if GPIO6 is low during reset. The C13 pin is

set to EMIF.SOE3 if GPIO6 is high during reset. The function of the C13 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO33

I/O/Z

C, D, E,

F, G, H,

Parallel general-purpose I/O. PGPIO33 is selected when GPIO6 is low during reset.

The PGPIO33 signal is configured as an input after reset.

EMIF.SOE3

O/Z

EMIF synchronous memory output-enable for CE3. EMIF.SOE3 is selected when

GPIO6 is high during reset. The EMIF.SOE3 signal is in a high-impedance state during

reset and is set to output after reset with an output value of 1.

The EMIF.SOE3 signal is intended for glueless FIFO interface.

C14

I/O/Z

F, G, H,

The C14 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO34 or external memory interface control signal

EMIF.HOLD. The function of the C14 pin is determined by the state of the GPIO6 pin

during reset. The C14 pin is set to PGPIO34 if GPIO6 is low during reset. The C14 pin is

set to EMIF.HOLD if GPIO6 is high during reset. The function of the C14 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO34

I/O/Z

F, G, H,

J, M

Parallel general-purpose I/O. PGPIO34 is selected when GPIO6 is low during reset.

The PGPIO34 signal is configured as an input after reset.

EMIF.HOLD

EMIF hold request. EMIF.HOLD is selected when GPIO6 is high during reset.

EMIF.HOLD is asserted by an external host to request control of the address, data, and

control signals.

C15

I/O/Z

The C15 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO35 or external memory interface control signal

EMIF.HOLDA. The function of the C15 pin is determined by the state of the GPIO6 pin

during reset. The C15 pin is set to PGPIO35 if GPIO6 is low during reset. The C15 pin is

set to EMIF.HOLDA if GPIO6 is high during reset. The function of the C15 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO35

I/O/Z

C, D, F,

G, H, M

Parallel general-purpose I/O. PGPIO35 is selected when GPIO6 is low during reset.

The PGPIO35 signal is configured as an input after reset.

EMIF.HOLDA

O/Z

G, H, M

EMIF hold acknowledge. EMIF.HOLDA is selected when GPIO6 is high during reset.

The EMIF.HOLDA signal is in a high-impedance state during reset and is set to output

after reset with an output value of ‘1’.

EMIF.HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state and

that the EMIF address, data, and control signals are in a high-impedance state, allowing

the external memory interface to be accessed by other devices.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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