TNETV2501INPGF datasheet(80/197 Pages) TI1

80 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.10.3

Module Behavior at Entering IDLE State

All transactions must be completed before entering the IDLE state. Table 3−24 lists the behavior of each

module before entering the IDLE state.

Table 3−24. Peripheral Behavior at Entering IDLE State

CLOCK DOMAIN

MODULES

MODULE BEHAVIOR AT ENTERING IDLE STATE

(ASSUMING THE IDLE CONTROL IS SET)

CPU

Enter IDLE after CPU stops pipeline.

CPU

Interrupt Controller

Enter IDLE after CPU stops.

CPU

IDLE Controller

Enter IDLE after CPU stops.

PLL Controller

Enter IDLE after CPU stops.

Master Port

DMA

Enter IDLE state after current DMA transfer to internal memory, EMIF, or

peripheral, or enter IDLE state immediately if no transfer exists.

DMA has function of Auto-wakeup/Idle with McBSP data transfer during

IDLE.

HPI

Enter IDLE state immediately. Software has to take care of HPI activity.

ICACHE

Enter IDLE state after current data transfer from EMIF or program fetch from

CPU finishes, or enter IDLE state immediately if no transfer and no access

exist.

External Bus Selection Register

Enter IDLE after CPU stops.

Timer Signal Selection Register

Enter IDLE after CPU stops.

CLKOUT Selection Register

Enter IDLE after CPU stops.

External Bus Control Register

Enter IDLE after CPU stops.

Clock Mode Control Register

Enter IDLE after CPU stops.

Timer0/1 and WDT

Enter IDLE state immediately

DSP/BIOS Timer

Enter IDLE state immediately

Peripheral

McBSP0/1

External Clock and Frame:

Enter IDLE state after current McBSP activity is finished or enter IDLE state

immediately if no activity exists. McBSP has function of Auto-wakeup/Idle

with DMA transfer during IDLE.

Internal Clock and Frame:

Enter IDLE state immediately if both transmitter and receiver are in reset

(XRST = 0 and RRST = 0). IDLE state not entered otherwise.

GPIO

Enter IDLE state immediately.

I2C

Enter IDLE state after current I2C activity is finished or enter IDLE state

immediately if no activity exists.

UART

Enter IDLE state after current UART activity is finished or enter IDLE state

immediately if no activity exists.

Parallel GPIO

Enter IDLE state immediately.

PLL divider

Enter IDLE state immediately.

Clock Generator

PLL core

Power-down state if set by software before IDLE

Clock Generator

Oscillator

Power-down state if set by software before IDLE

EMIF

Enter IDLE mode after current DMA transfer or enter IDLE mode

immediately if no activity exists.

TNETV2501INPGF Datasheet(PDF) 80 Page - Texas Instruments

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