TNETV2501INPGF datasheet(83/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.10.4.7 IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure

The internal oscillator of the 5501 will be woken up along with the CLOCK module through an NMI or an

enabled external interrupt. The source (INT0, INT1, INT2, INT3, or NMI) for the wake-up signal can be selected

through the use of the WKEN register. The maskable external interrupts must be enabled through IER0 and

IER1 prior to setting the 5501 to Idle 3 mode.

The 5501 has internal circuitry that will count down a predetermined number of clock cycles (41,032 reference

clock cycles) to allow the oscillator input to become stable after waking up from power-down state or reset.

When waking up from idle mode, program flow will start after the stabilization period of the oscillator has

expired (41 032 reference clock cycles).

To take the 5501 (including the internal oscillator) out of the idle 3 state, execute the following procedure:

External interrupt or NMI occurs (as specified in the WKEN register) and program flow begins after

41,032 reference clock cycles.

CPU wakes up.

Write ‘0’ to all bits in the ICR.

Execute the IDLE instruction.

All internal clocks are enabled and all modules come out of idle.

Write ‘0’ to the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR.

Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.

Set the PLLEN bit in PLLCSR to ‘1’.

All internal clocks will now come from the PLL core.

NOTE: Step 2 can be modified to only wake up certain modules, see previous sections for

more information on the wake-up procedures for the 5501 modules.

3.10.4.8 Summary of Wake-up Procedures

Table 3−25 summarizes the wake-up procedures.

Table 3−25. Wake-Up Procedures

ISTR

VALUE

CLOCK DOMAIN

STATUS

EXIT FROM IDLE

ICR

AFTER

WAKE-UP

ISTR

AFTER

WAKE-UP

xxx0xxx0

CPU − ON

Clock Generator − ON

Other − ON/OFF

1. DSP software modifies ICR

and executes “IDLE”

instruction

2. Reset

1. Modified value

2. All “0”

1. Updated to ICR modified

value after “IDLE”

instruction

2. All “0”

xxx0xxx1

CPU − OFF

Clock Generator − ON

Other − ON/OFF

1. Unmasked interrupt from

external or on-chip module

2. Reset

1. Not modified

2. All “0”

1. CPUIS, CLKIS, and

EMIFIS/XPORTIS/IPORTIS

are set to “0”

2. All “0”

xxx11111

CPU − OFF

Clock Generator − OFF

Other − OFF

1. Unmasked interrupt from

external

2. Reset

1. Not modified

2. All “0”

1. CPUIS, CLKIS, and

EMIFIS/XPORTIS/IPORTIS

are set to “0”

2. All “0”

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