TNETV2501INPGF datasheet(36/197 Pages) TI1

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Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Test Pins

TCK

C, J

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50%

duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are

clocked into the TAP controller, instruction register, or selected test data register on the

rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of

TCK. Refer to Section 3.17, Notice Concerning TCK, for important information regarding

this pin.

TDI

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into

the selected register (instruction or data) on a rising edge of TCK.

TDO

O/Z

IEEE standard 1149.1 test data output. The contents of the selected register (instruction

or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance

state except when the scanning of data is in progress.

TMS

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial

control input is clocked into the TAP controller on the rising edge of TCK.

TRST

C, L, K

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1

scan system control of the operations of the device. If TRST is not connected or driven

low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are

ignored. Pin has an internal pulldown device.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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