TNETV2501INPGF datasheet(27/197 Pages) TI1

27 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Parallel Port − Control Pins (Continued)

C10

I/O/Z

C, D, E,

F, G, H,

The C10 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO30 or external memory interface control signal

EMIF.BE2. The function of the C10 pin is determined by the state of the GPIO6 pin during

reset. The C10 pin is set to PGPIO30 if GPIO6 is low during reset. The C10 pin is set to

EMIF.BE2 if GPIO6 is high during reset. The function of the C10 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO30

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO30 is selected when GPIO6 is low during reset.

The PGPIO30 signal is configured as an input after reset.

EMIF.BE2

O/Z

EMIF byte-enable 2 control. EMIF.BE2 is selected when GPIO6 is high during reset. The

EMIF.BE2 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

C11

I/O/Z

C, D, E,

F, G, H,

The C11 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO31 or external memory interface control signal

EMIF.BE3. The function of the C11 pin is determined by the state of the GPIO6 pin during

reset. The C11 pin is set to PGPIO31 if GPIO6 is low during reset. The C11 pin is set to

EMIF.BE3 if GPIO6 is high during reset. The function of the C11 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO31

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO31 is selected when GPIO6 is low during reset.

The PGPIO31 signal is configured as an input after reset.

EMIF.BE3

O/Z

EMIF byte-enable 3 control. EMIF.BE3 is selected when GPIO6 is high during reset. The

EMIF.BE3 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

C12

I/O/Z

C, D, E,

F, G, H,

The C12 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO32 or external memory interface control signal

EMIF.SDCKE. The function of the C12 pin is determined by the state of the GPIO6 pin

during reset. The C12 pin is set to PGPIO32 if GPIO6 is low during reset. The C12 pin is

set to EMIF.SDCKE if GPIO6 is high during reset. The function of the C12 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO32

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO32 is selected when GPIO6 is low during reset.

The PGPIO32 signal is configured as an input after reset.

EMIF.SDCKE

O/Z

EMIF SDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high during reset.

The EMIF.SDCKE signal is in a high-impedance state during reset and is set to output

after reset with an output value of 1.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

TNETV2501INPGF Datasheet(PDF) 27 Page - Texas Instruments

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