TNETV2501INPGF datasheet(26/197 Pages) TI1

26 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Parallel Port − Control Pins (Continued)

I/O/Z

C, D, E,

F, G, H,

The C7 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO27 or external memory interface control signal

EMIF.CE3. The function of the C7 pin is determined by the state of the GPIO6 pin during

reset. The C7 pin is set to PGPIO27 if GPIO6 is low during reset. The C7 pin is set to

EMIF.CE3 if GPIO6 is high during reset. The function of the C7 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO27

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO27 is selected when GPIO6 is low during reset.

The PGPIO27 signal is configured as an input after reset.

EMIF.CE3

O/Z

EMIF chip-select for memory space CE3. EMIF.CE3 is selected when GPIO6 is high

during reset. The EMIF.CE3 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

I/O/Z

C, D, E,

F, G, H,

The C8 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO28 or external memory interface control signal

EMIF.BE0. The function of the C8 pin is determined by the state of the GPIO6 pin during

reset. The C8 pin is set to PGPIO28 if GPIO6 is low during reset. The C8 pin is set to

EMIF.BE0 if GPIO6 is high during reset. The function of the C8 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO28

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO28 is selected when GPIO6 is low during reset.

The PGPIO28 signal is configured as an input after reset.

EMIF.BE0

O/Z

EMIF byte-enable 0 control. EMIF.BE0 is selected when GPIO6 is high during reset. The

EMIF.BE0 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

I/O/Z

C, D, E,

F, G, H,

The C9 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO29 or external memory interface control signal

EMIF.BE1. The function of the C9 pin is determined by the state of the GPIO6 pin during

reset. The C9 pin is set to PGPIO29 if GPIO6 is low during reset. The C9 pin is set to

EMIF.BE1 if GPIO6 is high during reset. The function of the C9 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO29

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO29 is selected when GPIO6 is low during reset.

The PGPIO29 signal is configured as an input after reset.

EMIF.BE1

O/Z

EMIF byte-enable 1 control. EMIF.BE1 is selected when GPIO6 is high during reset. The

EMIF.BE1 signal is in a high-impedance state during reset and is set to output after reset

with an output value of 1.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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