TNETV2501INPGF datasheet(92/197 Pages) TI1

92 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.10.7.6 Master IDLE Status Register (MISR)

Reserved

R, 00000000

Reserved

HPI

DMA

R, 000000

R, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−31. Master IDLE Status Register Layout (0x9403)

Table 3−32. Master IDLE Status Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15−2

00000000000000

Reserved

HPI

HPI bit

HPI = 0:

HPI is active

HPI = 1:

HPI is in IDLE status

DMA

DMA bit

DMA = 0:

DMA is active

DMA = 1:

DMA is in IDLE status

3.11 General-Purpose I/O (GPIO)

The 5501 includes an 8-bit I/O port solely for general-purpose input and output. Several dual-purpose

(multiplexed) pins complement the dedicated GPIO pins. The following sections describe the 8-bit GPIO port

as well as the dual GPIO functions of the Parallel Port Mux and Host Port Mux pins.

3.11.1

General-Purpose I/O Port

The general-purpose I/O port consists of eight individually bit-selectable I/O pins GPIO0 (LSB) through GPIO7

(MSB). The I/O port is controlled using two registers—IODIR and IODATA—that can be accessed by the CPU

or by the DMA, via the peripheral bus controller. The General-Purpose I/O Direction Register (IODIR) is

mapped at address 0x3400, and the General-Purpose I/O Data Register (IODATA) is mapped at address

0x3401.

Figure 3−32 and Figure 3−33 show the bit layout of IODIR and IODATA, respectively. Table 3−33 and

Table 3−34 describe the bit fields of these registers.

TNETV2501INPGF Datasheet(PDF) 92 Page - Texas Instruments

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