TNETV2501INPGF datasheet(65/197 Pages) TI1

65 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.9.4.1

C55x Subsystem Clock Group

Changes to the PLL Control Register (PLLCSR), the PLL Divider0 Register (PLLDIV0), and the PLL Multiplier

to set the PLL to a specific value:

Switch to bypass mode by setting the PLLEN bit to 0.

Set the PLL to its reset state by setting the PLLRST bit to 1.

Change the PLL setting through the PLLM and PLLDIV0 bits.

Wait for 1

µs.

Release the PLL from its reset state by setting PLLRST to 0.

Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.

Switch back to PLL mode by setting the PLLEN bit to 1.

The frequency of the C55x Subsystem Clock Group can be up to 300 MHz.

3.9.4.2

Fast Peripherals Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Fast Peripherals Clock Group.

The PLLDIV1 value of the PLL Divider1 Register (PLLDIV1) should not be set in a manner that makes the

frequency for this clock group greater than 150 MHz. There must be no activity in the modules included in the

Fast Peripherals Clock Group when the value of PLLDIV1 is being changed. It is recommended that the fast

peripheral modules be put in IDLE mode before changing the PLLDIV1 value.

3.9.4.3

Slow Peripherals Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Slow Peripherals Clock

Group. The PLLDIV2 value of the PLL Divider2 Register (PLLDIV2) should not be set in a manner that makes

the frequency for this clock group greater than 150 MHz or greater than the frequency of the Fast Peripherals

Clock Group. There must be no activity in the modules included in the Slow Peripherals Clock Group when

the value of PLLDIV2 is being changed. It is recommended that the slow peripheral modules be put in IDLE

mode before changing the PLLDIV2 value.

3.9.4.4

External Memory Interface Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the External Memory Interface

Clock Group. The PLLDIV3 value of the PLL Divider3 Register (PLLDIV3) should not be set in a manner that

makes the frequency for this clock group greater than 100 MHz or greater than the frequency of the Fast

Peripherals Clock Group, whichever is smaller. If an external clock is used, the clock on the ECLKIN pin can

be up to 100 MHz and the output of divider 3 can be set equal to or lower than the frequency of the Fast

Peripherals Clock Group. There must be no external memory accesses when the value of PLLDIV3 is being

changed, this means that the value of PLLDIV3 cannot be changed by a program that is being executed from

external memory. It is recommended that the EMIF be put in IDLE mode before changing the PLLDIV3 value.

TNETV2501INPGF Datasheet(PDF) 65 Page - Texas Instruments