TNETV2501INPGF datasheet(31/197 Pages) TI1

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Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Host Port − Control Pins (Continued)

HC1

I/O/Z

F, G, H,

The HC1 pin of the Host Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO45 or host-port interface (HPI) signal HPI.HBIL. The

function of the HC1 pin is determined by the state of the GPIO6 pin during reset. The HC1

pin is set to PGPIO45 if GPIO6 is low during reset. The HC1 pin is set to HPI.HBIL if GPIO6

is high during reset. The function of the HC1 pin will be set once the device is taken out of

reset (RESET pin transitions from a low to high state).

PGPIO45

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO45 is selected when GPIO6 is low during reset.

The PGPIO45 signal is configured as an input after reset.

HPI.HBIL

Host byte identification. HPI.HBIL is selected when GPIO6 is high during reset. The

HPI.HBIL signal is configured as an input after reset.

In multiplexed mode, the host must use HPI.HBIL to identify the first and second bytes of

the host cycle.

HPI Pins

HCNTL0

I/O/Z

F, G, H,

HPI access control pins. The four binary states of the HCNTL0 and HCNTL1 pins

determine which HPI register is being accessed by the host (HPIC, HPID with

HCNTL1

I/O/Z

F, G, H,

determine which HPI register is being accessed by the host (HPIC, HPID with

autoincrementing, HPIA, or HPID). The HCNTL0 and HCNTL1 pins are configured as

inputs after reset.

HCS

I/O/Z

C, F, G,

H, J

HPI chip-select. HCS must be low for the HPI to be selected by the host. The HCS pin is

configured as an input after reset.

A host must not initiate transfer requests until the HPI has been brought out of reset,

see Section 3.7, Host-Port Interface (HPI), for more details.

HR/W

I/O/Z

F, G, H,

Host read- or write-select. HR/W indicates whether the current access is to be a read or

write operation. The HR/W pin is configured as an input after reset.

HDS1

C, G,

Host data strobe pins. The HDS1 and HDS2 pins are used for strobing data in and out of

the HPI. The HDS1 and HDS2 pins are configured as inputs after reset.

HDS2

C, G,

H, J

the HPI. The HDS1 and HDS2 pins are configured as inputs after reset.

A host must not initiate transfer requests until the HPI has been brought out of reset,

see Section 3.7, Host-Port Interface (HPI), for more details.

HRDY

O/Z

F, J, M

Host ready (from DSP to host). The HRDY pin informs the host when the HPI is ready for

the next transfer. The HRDY pin is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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