TNETV2501INPGF datasheet(15/197 Pages) TI1

15 / 197 page

Features

December 2002 − Revised November 2008

SPRS206K

TMS320VC5501 Features

D High-Performance, Low-Power, Fixed-Point

TMS320C55x

 Digital Signal

Processor (DSP)

− 3.33-ns Instruction Cycle Time for

300-MHz Clock Rate

− 16K-Byte Instruction Cache (I-Cache)

− One/Two Instructions Executed per Cycle

− Dual Multipliers [Up to 600 Million

Multiply-Accumulates Per Second

(MMACS)]

− Two Arithmetic/Logic Units (ALUs)

− One Program Bus, Three Internal

Data/Operand Read Buses, and Two

Internal Data/Operand Write Buses

D Instruction Cache (16K Bytes)

D 16K x 16-Bit On-Chip RAM That is

Composed of Four Blocks of 4K

× 16-Bit

Dual-Access RAM (DARAM) (32K Bytes)

D 16K × 16-Bit One-Wait-State On-Chip ROM

(32K Bytes)

D 8M × 16-Bit Maximum Addressable External

Memory Space

D 32-Bit External Parallel Bus Memory

Supporting External Memory Interface

(EMIF) With General-Purpose Input/Output

(GPIO) Capabilities and Glueless Interface

to:

− Asynchronous Static RAM (SRAM)

− Asynchronous EPROM

− Synchronous DRAM (SDRAM)

− Synchronous Burst RAM (SBRAM)

D Emulation/Debug Trace Capability Saves

Last 16 Program Counter (PC)

Discontinuities and Last 32 PC Values

D Programmable Low-Power Control of Six

Device Functional Domains

D On-Chip Peripherals

− Six-Channel Direct Memory Access

(DMA) Controller

− Two Multichannel Buffered Serial Ports

(McBSPs)

− Programmable Analog Phase-Locked

Loop (APLL) Clock Generator

− General-Purpose I/O (GPIO) Pins and a

Dedicated Output Pin (XF)

− 8-Bit Parallel Host-Port Interface (HPI)

− Four Timers

− Two 64-Bit General-Purpose Timers

− 64-Bit Programmable Watchdog Timer

− 64-Bit DSP/BIOS

 Counter

− Inter-Integrated Circuit (I2C) Interface

− Universal Asynchronous Receiver/

Transmitter (UART)

D On-Chip Scan-Based Emulation Logic

D IEEE Std 1149.1† (JTAG) Boundary Scan

Logic

D Packages:

− 176-Terminal LQFP (Low-Profile Quad

Flatpack) (PGF Suffix)

− 201-Terminal MicroStar BGA

 (Ball Grid

Array) (GZZ and ZZZ Suffixes)

D 3.3-V I/O Supply Voltage

D 1.26-V Core Supply Voltage

TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

TNETV2501INPGF Datasheet(PDF) 15 Page - Texas Instruments

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