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TNETV2501INPGF Datasheet(PDF) 20 Page - Texas Instruments |
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TNETV2501INPGF Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 197 page  Introduction 20 December 2002 − Revised November 2008 SPRS206K Table 2−3. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments†‡ PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME 1 GPIO6 45 HCNTL1 89 A19 133 D16 2 GPIO4 46 HCNTL0 90 A18 134 D15 3 GPIO2 47 VSS 91 VSS 135 D14 4 GPIO1 48 HR/W 92 A17 136 D13 5 GPIO0 49 HDS2 93 A16 137 D12 6 TIM1 50 CVDD 94 DVDD 138 D11 7 TIM0 51 HDS1 95 A15 139 D10 8 INT0 52 HRDY 96 A14 140 D9 9 CVDD 53 DVDD 97 VSS 141 DVDD 10 INT1 54 CLKOUT 98 A13 142 D8 11 INT2 55 XF 99 A12 143 D7 12 DVDD 56 VSS 100 CVDD 144 VSS 13 INT3 57 C15 101 A11 145 D6 14 NMI/WDTOUT 58 C14 102 A10 146 D5 15 IACK 59 HINT 103 A9 147 D4 16 VSS 60 PVDD 104 A8 148 CVDD 17 CLKR0 61 NC 105 DVDD 149 D3 18 DR0 62 X1 106 A7 150 D2 19 FSR0 63 X2/CLKIN 107 A6 151 D1 20 CLKX0 64 EMIFCLKS 108 A5 152 D0 21 CVDD 65 VSS 109 VSS 153 VSS 22 DX0 66 C13 110 A4 154 EMU1/OFF 23 FSX0 67 C12 111 A3 155 EMU0 24 CLKR1 68 C11 112 A2 156 TDO 25 DR1 69 C10 113 CVDD 157 VSS 26 FSR1 70 C9 114 D31 158 TDI 27 DX1 71 C8 115 D30 159 TRST 28 CLKX1 72 C7 116 D29 160 TCK 29 VSS 73 VSS 117 VSS 161 TMS 30 FSX1 74 ECLKIN 118 D28 162 RESET 31 TEST§ 75 ECLKOUT2 119 D27 163 HPIENA 32 NC 76 ECLKOUT1 120 D26 164 HD7 33 CVDD 77 CVDD 121 CVDD 165 CVDD 34 RX 78 C6 122 D25 166 HD6 35 GPIO5 79 C5 123 D24 167 HD5 36 DVDD 80 DVDD 124 DVDD 168 DVDD 37 TX 81 C4 125 D23 169 HD4 38 GPIO3 82 C3 126 D22 170 HD3 39 VSS 83 VSS 127 D21 171 CVDD 40 SCL 84 C2 128 D20 172 HD2 41 SDA 85 C1 129 D19 173 HD1 42 HC1 86 C0 130 VSS 174 VSS 43 HC0 87 A21 131 D18 175 HD0 44 HCS 88 A20 132 D17 176 GPIO7¶ † CVDD is core VDD, DVDD is I/O VDD, and PVDD is PLL VDD. ‡ NC indicates “no connect”. § The TEST pin is reserved for internal testing. It should be left unconnected. ¶ The GPIO7 pin must be low at the rising edge of the reset signal for the device to operate properly. |
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