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ADDR10 Datasheet(PDF) 15 Page - List of Unclassifed Manufacturers

Part # ADDR10
Description  Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins
PDF  68 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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E t h e rn et interfa ce MAC
ww w.d i gi .c om
11
Ethernet interface MAC
Note:
ENDEC values for general-purpose output and TXD refer to bits in the Ethernet General
Control register. ENDEC values for general-purpose input and RXD refer to bits in the
Ethernet General Status register.
In this table, GP designates general-purpose.
Ethernet interface MAC signal descriptions
The Ethernet MII (media independent interface) provides the connection between the Ethernet PHY
and the MAC (media access controller).
Symbol
Pin
I/O
OD
Description
MII
ENDEC
MII
ENDEC
MDC
GP output
D10
O
2
MII
management
clock
State of (LPBK bit XOR
(Mode=SEEQ))
MDIO
GP output
B10 U
I/O
2
MII data
State of UTP_STP bit
TXCLK
C10
I
TX clock
TXD3
GP output
A12
O
2
TX data 3
State of AUI_TP[0] bit
TXD2
GP output
B11
O
2
TX data 2
State of AUI_TP[1] bit
TXD1
GP output
D11
O
2
TX data 1
Inverted state of PDN bit, open
collector
TXD0
TXD
A11
O
2
TX data 0
Transmit data
TXER
GP output
A13
O
2
TX code error
State of LNK_DIS_ bit
TXEN
B12
O
2
TX enable
TXCOL
A14
I
Collision
RXCRS
D12
I
Carrier sense
RXCLK
C12
I
RX clock
RXD3
GP input
D14
I
RX data 3
Read state in bit 12
RXD2
GP input
B15
I
RX data 2
Read state in bit 15
RXD1
GP input
A15
I
RX data 1
Read state in bit 13
RXD0
RXD
B13
I
RX data 0
Receive data
RXER
GP input
C15
I
RX error
Read state in bit 11
RXDV
GP input
D15
I
RX data valid
Read state in bit 10



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