ADDR10 datasheet(31/68 Pages) ETC2

31 / 68 page

Oscilla to r Characteristics

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Oscillator Characteristics

Figure 8 illustrates the recommended oscillator circuit details.

Rise/fall time. The max rise/fall time on the system clock input pin is 1.5ns when used

with an external oscillator.

Duty cycle. The duty cycle is system-dependent with an external oscillator. It affects the

setup and hold times of signals that change in the falling clock edges, such as WE_/OE_.

Recommendation: Use a 3.3V, 50±10% duty cycle oscillator with a 100 ohm series resistor

at the output. The PLLs can handle a 25% duty cycle clock (minimum high/low time

4.5nS).

Figure 8: Oscillator circuit details

CS[4:0]_, CAS[3:0], RW_, WE_, OE_

0.137

MDC, TXD[3:0], TXER, TXEN, TDO

0.274

Signal

Derating (ns/pF)

Table 8: Output buffer derating by load capacitance

3R3V

SCANEN_

PLL enabled - U1 & R2 IN, R1 OUT

10pF

A 18.432MHz crystal or 55.296MHz

oscillator allows full speed operation.

0 OHM

LVC04

RESET_

K14

3R3V

100nF

10pF

0 OHM

PLL bypassed - U1 & R2 OUT, R1 IN

10K

SM_Oscillator

VCC

GND

TEST

OUT

K12

NS7520

R11

100 OHM

XTAL1

A10

Rise time = 18ns;

0.8V to 2.0V

XTAL1

L13

RESET_

XTAL2

Optional 36.864-55.296MHz Oscillator

TB1

XTAL2

10-20MHz

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