Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

ADDR10 Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers

Part # ADDR10
Description  Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ETC2 [List of Unclassifed Manufacturers]
Direct Link  
Logo ETC2 - List of Unclassifed Manufacturers

ADDR10 Datasheet(HTML) 22 Page - List of Unclassifed Manufacturers

Back Button ADDR10 Datasheet HTML 18Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 19Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 20Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 21Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 22Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 23Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 24Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 25Page - List of Unclassifed Manufacturers ADDR10 Datasheet HTML 26Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 68 page
background image
NS 75 20 mo dul es
18
NS 75 20 Da ta shee t
03 /2 00 6
NS7520 modules
CPU module
The CPU uses an ARM7TDMI core processor. The ARM architecture is based on Reduced Instruction
Set Computer (RISC) principles, which result in high instruction throughput and impressive real-
time interrupt response for a small, cost-effective circuit. For more information about ARM7TDMI,
see the ARM7TDMI Data Sheet from ARM Ltd. (www.arm.com).
GEN module
The GEN module provides the NS7520 with its main system control functions, as well as these
features:
Two programmable timers with interrupt
One programmable bus-error timer
One programmable watchdog timer
Two 8-bit programmable general-purpose I/O ports
System (SYS) module
The system module provides the system clock (SYS_CLK) and system reset (SYS_RESET) resources.
The system control signals determine the basic operation of the chip:
Signal mnemonic
Signal name
Description
{XTALA1, XTALA2}
Clock source
Operate in one of two ways:
The signals are affixed with a 10-20 MHz parallel mode
quartz crystal or crystal oscillator and the appropriate
components per the component manufacturer.
XTALA1 is driven with a clock signal and XTALA2 is
left open.
{PLLVDD, PLLVSS}
PLL power
Provide an isolated power supply for the PLL.
RESET_
Chip reset
Active low signal asserted to initiate a hardware reset of the
chip.
{TDI, TDO, TNS,
TRST_, TCK}
JTAG interface
Provide a JTAG interface for the chip. This interface is used
for both boundary scan and ICE control of the internal
processor.
{PLLTEST_, BISTEN_,
SCANEN_}
Chip mode
Encoded to determine the chip mode.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com