ADDR10 datasheet(18/68 Pages) ETC2

18 / 68 page

Ge ne r a l P u rp ose I / O

NS 75 20 Da ta shee t

03 /2 00 6

Notes:

RESET output indicates the reset state of the NS7520. PORTC4 persists beyond the negation of

RESET_ for approximately 512 clock cycles if the PLL is disabled. When the PLL is enabled,

PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds

times the ratio of the VCO to XTALA.

This GPIO is left in output mode active following a hardware RESET.

PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to be synchronous

to any clock. The interrupt remains active until cleared by a change in the input signal level.

PORTC5

RTSB_

REJECT_

F15 U I/O

Channel 2 RTS_

CAM reject

PORTC41

RXCB/RIB_/

OUT1B_

RESET_

F12 U I/O

Pgm’able Out/

Channel 2

RXCLK/Channel 2

ring signal/

Channel 2 SPI

clock (CLK)

RESET output

PORTC32

RXDB

LIRQ3/

DACK2_

F13 U I/O

Channel 2 RXD

Level sensitive IRQ /

DMA channel 4/6

ACK

PORTC22

DSRB_

LIRQ2/RPSF_ E15 U I/O

Channel 2 DSR_

Level sensitive IRQ/

CAM request

PORTC12

CTSB_

LIRQ1/

DONE2_(O)

E12 U I/O

Channel 2 CTS_

Level sensitive IRQ /

DMA channel 4/6

DONE_Out

PORTC02

TXCB/

OUT2B_/

DCDB_

LIRQ0/

DONE2_(I)

E14 U I/O

Pgm’able Out/

Channel 2 DCD/

Channel 2 SPI

enable (SEL_)/

Channel 2 TXCLK

Level sensitive IRQ /

DMA channel 4/6

DONE_In

GPIO signal

Serial

signal

Other

signal

I/O

Serial channel

description

Other

description

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