ADDR10 datasheet(26/68 Pages) ETC2

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NS75 20 b ootstra p ini t i a li zation

NS 75 20 Da ta shee t

03 /2 00 6

NS7520 bootstrap initialization

Many internal NS7520 features are configured when the RESET pin is asserted. The address bus

configures the appropriate control register bits at powerup. This table shows which bits control

which functions:

JTAG

The NS7520 provides full support for 1149.1 JTAG boundary scan testing. All NS7520 pins can be

controlled using the JTAG interface port. The JTAG interface provides access to the ARM7TDMI

debug module when the appropriate combination of PLLTST_, BISTEN_, and SCANEN_ is selected (as

shown in Table 3: "NS7520 test modes").

ARM Debug

The ARM7TDMI core uses a JTAG TAP controller that shares the pins with the TAP controller used for

1149.1 JTAG boundary scan testing. To enable the ARM7TDMI TAP controller,

{PLLTST_,BISTEN_,SCANEN_}

must be set as shown in Table 3: "NS7520 test modes".

Address bit

Name

Description

ADDR[27]

Endian configuration

0 Little Endian configuration

1 Big Endian configuration

ADDR[26]

CPU bootstrap

0 CPU disabled; GEN_BUSER=1

1 CPU enabled; GEN_BUSER=0

ADDR[24:23]

CS0/MMCR[19:18] setting

8-bit SRAM, 63 wait-states/b00

32-bit SRAM, 63 wait-states/b01

32-bit SRAM

16-bit SRAM, 63 wait-states/b11

ADDR[19:9]

GEN_ID setting

GEN_ID=A[19:09],default=’h3ff

ADDR[8:7]

PLL IS setting

IS=A[8:7], default=’b10

ADDR[6:5]

PLL FS setting

FS=A[6:5], default=’b00

ADDR[4:0]

PLL ND setting

ND=A[4:0], default=’b01011

Table 3: NS7520 test modes

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