ADDR10 datasheet(33/68 Pages) ETC2

33 / 68 page

Reset_timing

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Reset_timing

From a cold start, RESET_ must be asserted until all power supplies are above their specified

thresholds. An additional 8 microseconds is required for oscillator settling time (allow 40ms for

crystal startup).

Due to an internal three flip-flop delay on the external RESET_ signal, after the oscillator is

settled, RESET_ must be asserted for three periods of the XTALA1 clock in these situations:

Before release of reset after application of power

While valid power is maintained to initiate hot reset (reset while power is at or above

specified thresholds)

Before loss of valid power during power outage/power down

The PORTC4 output indicates the reset state of the chip. PORTC4 persists beyond the negation of

RESET_ for approximately 512 system clock cycles if the PLL is disabled. When the PLL is enabled,

PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds times

the ratio of the VCO to XTALA.

Reset timing parameters

Num

Description

Min

Typ

Max

Units

Power valid before reset negated

Note: RESET_ should remain low

for at least 40ms after power

reaches 3.0V.

Reset asserted after power valid

TXTALA1

Reset asserted while power valid

TXTALA1

Reset asserted before power invalid

TXTALA1

VDD, VCC

XTALA1

RESET_

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