ADDR10 datasheet(23/68 Pages) ETC2

23 / 68 page

BB us mod u le

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The NS7520 clock module creates the BCLK and FXTAL signals. Both signals are used internally, but

BCLK can also be accessed at ball A6 by setting the BCLKD field in the System Control register to 0.

BCLK functions as the system clock and provides the majority of the NS7520’s timing.

FXTAL provides the timing for the DRAM refresh counter, can be selected instead of BCLK

to provide timing for the watchdog timer, the two internal timers, and the Serial module.

BBus module

The BBus module provides the data path among NS7520 internal modules. This module provides the

address and data multiplexing logic that supports the data flow through the NS7520. The BBus

module is the central arbiter for all the NS7520 bus masters and, once mastership is granted,

handles the decoding of each address to one (or none) of the NS7520 modules.

Memory module (MEM)

The MEM module provides a glueless interface to external memory devices such as Flash, DRAM,

and EEPROM. The memory controller contains an integrated DRAM controller and supports five

unique chip select configurations.

The MEM module monitors the BBus interface for access to the bus module; that is, any access not

addressing internal resources. If the address to be used corresponds to a Base Address register in

the MEM module, the MEM module provides the memory access signals and responds to the BBus

with the necessary completion signal.

The MEM module can be configured to interface with FP, EDO, or SDRAM (synchronous DRAM),

although the NS7520 cannot interface with more than one device type at a time.

DMA controller

The NS7520 contains one DMA controller, with 13 DMA channels. Each DMA channel moves blocks of

data between memory and a memory peripheral.

The DMA controller supports both fly-by operations and memory-to-memory operations:

When configured for fly-by operation, the DMA controller transfers data between one of the

NS7520 peripherals and a memory location.

When configured for memory-to-memory operations, the DMA controller uses a temporary

holding register between read and write operations. Two memory cycles are executed.

Ethernet controller

The Ethernet controller provides the NS7520 with one IEEE 802.3u compatible Ethernet interface.

The Ethernet interface includes the Ethernet front-end (EFE) and media access controller (MAC).

The Ethernet module supports both media independent interface (MII) and ENDEC modes.

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