ADDR10 datasheet(65/68 Pages) ETC2

65 / 68 page

Serial in te rn al/external tim i ng

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Serial internal/external timing

Operating conditions:

Note:

SPI timing diagrams are in Chapter 10, "Serial Controller Module." See Figure 25, "SPI

master mode 0 and 1 two-byte transfer," on page 219 and Figure 26, "SPI slave mode 0

and 1 two-byte transfer," on page 222. Only SPI modes 0 and 1 are supported.

Serial internal timing characteristics

Serial external timing characteristics

Temperature:

-15.00 (min)

110.00 (max)

Voltage:

1.60 (min)

1.40 (max)

Output load:

25.0pf

Input drive:

CMOS buffer

Num

Description

Min

Max

Unit

SCLK to ENABLE high

TSCLK

SCLK to TXD (PORTA7/C7)

1 TSYS*ns

RXD (PORTA3/C3) setup to SCLK

RXD hold to SCLK

* The TSYS parameter represents one period of the internal system clock.

Num

Description

Min

Max

Unit

SCLK frequency

MHz

SCLK duty cycle

SCLK to ENABLE

TSCLK

SCLK to TXD (PORTA7/C7)

2TSYS*ns

RXD (PORTA3/C3) setup to SCLK

RXD hold to SCLK

1.5

* The TSYS parameter represents one period of the internal system clock.

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